이 특허에 인용된 특허 (61)

1. Parlour David B. (Pittsburgh PA) Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA) Young Edel M. (Palo Alto CA), Adaptive programming method for antifuse technology.

   상세보기
2. Trimberger,Steven M.; Bapat,Shekhar; Wells,Robert W.; Patrie,Robert D.; Lai,Andrew W., Application-specific methods for testing molectronic or nanoscale devices.

   상세보기
3. Earl A. Killian ; Ricardo E. Gonzalez ; Ashish B. Dixit ; Monica Lam ; Walter D. Lichtenstein ; Christopher Rowen ; John C. Ruttenberg ; Robert P. Wilson ; Albert Ren-Rui Wang ; Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.

   상세보기
4. Betz, Vaughn; Rose, Jonathan, Automatic generation of programmable logic device architectures.

   상세보기
5. Nixon,Gregor; Jervis,Mark; Pan,Zhengjun; Silva,Gihan De; Perry,Steven, Chip debugging using incremental recompilation.

   상세보기
6. Beausang James ; Ellingham Chris ; Walker Robert, Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design.

   상세보기
7. Eng Tommy K., Creating optimized physical implementations from high-level descriptions of electronic design using placement based information.

   상세보기
8. Tommy K. Eng, Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information.

   상세보기
9. Rupp, Charle' R.; Garverick, Timothy L.; Arnold, Jeffrey, Design methodology for merging programmable logic into a custom IC.

   상세보기
10. Zirojevic,Srdan; White,Jason; Rust,Scott; Liang,Jucao, Dynamically determining a route through one or more switch devices at program execution time.

    상세보기
11. Singh, Harbinder; Martin, Denis; Ajjarapu, Srinivas; Walker, Robert, Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics.

    상세보기
12. Tsay Ren-Song (Palo Alto CA) Chang Chwen-Cher (Fremont CA), Electronic design automation tool for the design of a semiconductor integrated circuit chip.

    상세보기
13. Herrmann Alan L. ; Nugent Greg P., Embedded logic analyzer for a programmable logic device.

    상세보기
14. McGowan John E., Field programmable gate array with mask programmed analog function circuits.

    상세보기
15. Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.

    상세보기
16. Heimlich Michael C. ; St. Hilaire Kenneth R., Hierarchical adaptive state machine for emulating and augmenting software.

    상세보기
17. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.

    상세보기
18. Muradali, Fidel; Jaarsma, Neal C., Integrated circuit with scan test structure.

    상세보기
19. Pierce Kerry M. ; Erickson Charles R. ; Huang Chih-Tsung ; Wieland Douglas P., Interconnect architecture for field programmable gate array using variable length conductors.

    상세보기
20. Wong, Dale, Interconnection network for a field programmable gate array.

    상세보기
21. Borer,Terry P.; Quan,Gabriel; Brown,Stephen D.; Singh,Deshanand P.; Sanford,Chris; Betz,Vaughn; Pantofaru,Caroline; Swartz,Jordan, Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices.

    상세보기
22. Prakash S. Arunachalam ; Heming Chan, Method and apparatus for layout-constrained global routing.

    상세보기
23. Parlour David B., Method and apparatus for making incremental changes to an integrated circuit design.

    상세보기
24. Ara Markosian ; Yaacov (Jacob) Greidinger ; Siu-Tong Hui ; Sedrak Sargisian, Method and apparatus for optimizing electronic design.

    상세보기
25. Beausang James (Mountain View CA) Wagner Kenneth (Sunnyvale CA) Walker Robert (Boulder CO), Method and apparatus for performing partial unscan and near full scan within design for test applications.

    상세보기
26. Singh, Deshanand P.; Brown, Stephen D.; Borer, Terry P.; Sanford, Chris; Quan, Gabriel, Method and apparatus for placement of components onto programmable logic devices.

    상세보기
27. Blodget, Brandon J., Method and apparatus for pre-routing dynamic run-time reconfigurable logic cores.

    상세보기
28. Garnett, Robert E.; Kerzman, Joseph P.; Rezek, James E.; Aubel, Mark D., Method and apparatus for selectively viewing nets within a database editor tool.

    상세보기
29. Morgan David Allen, Method and apparatus for specifying multiple power domains in electronic circuit designs.

    상세보기
30. Nam, Gi-Joon; Kalman, Sandor S.; Anderson, Jason H.; Jayaraman, Rajeev; Nag, Sudip K.; Zhuang, Jennifer, Method and apparatus for testing routability.

    상세보기
31. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.

    상세보기
32. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.

    상세보기
33. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.

    상세보기
34. Russell B. Segal, Method and system for circuit design top level and block optimization.

    상세보기
35. Wang, Chuan-Yu; Wang, Ping-Hann Peter; Jiang, Yi-Min, Method and system for genetic algorithm based power optimization for integrated circuit designs.

    상세보기
36. Schiefele, Walter P.; Krueger, Robert O., Method for creating circuit redundancy in programmable logic devices.

    상세보기
37. Fung, Ryan; Padalia, Ketan, Method for mapping logic design memory into physical memory device of a programmable logic device.

    상세보기
38. Trimberger Stephen M., Method for tolerating defective logic blocks in programmable logic devices.

    상세보기
39. Guy Dupenloup FR, Method of handling macro components in circuit design synthesis.

    상세보기
40. Betz, Vaughn Timothy; Galloway, David Reid, Method of optimizing the design of electronic systems having multiple timing constraints.

    상세보기
41. Guruswamy Mohankumar ; Dulitz Daniel Wesley ; Fernandez Andrea ; Raman Srilata ; Maziasz Robert L., Method of routing an integrated circuit.

    상세보기
42. Roy Kaushik (West Lafayette IN) Nag Sudip K. (Pittsburgh PA), Method of segmenting an FPGA channel architecture for maximum routability and performance.

    상세보기
43. Mason, Jeffrey M.; Lass, Steve E.; Talley, Bruce E.; Bennett, David W., Modular design method and system for programmable logic devices.

    상세보기
44. Chaudhary Kamal ; Nag Sudip K., Post-placement residual overlap removal method for core-based PLD programming process.

    상세보기
45. Khoche Ajay ; Singh Harbinder ; Goswami Dhiraj ; Martin Denis, Pre-synthesis test point insertion.

    상세보기
46. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.

    상세보기
47. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.

    상세보기
48. Agrawal Om P. (Los Altos CA) Wright Michael J. (Boulder CO), Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses.

    상세보기
49. Wells, Robert W.; Patrie, Robert D.; Thorne, Eric J.; Matera, Michael M., Providing fault coverage of interconnect in an FPGA.

    상세보기
50. Beausang James, Scan segment processing within hierarchical scan architecture for design for test applications.

    상세보기
51. Cliff Richard G. ; Sung Chiakang, Segmented localized conductors for programmable logic devices.

    상세보기
52. Okabe Masatomi (Itami JPX), Semiconductor integrated circuit device with reduced clock signal line noise.

    상세보기
53. Noll Mark D. ; Scott Kenneth E. ; Walker Robert L., System and method for generating effective layout constraints for a circuit design or the like.

    상세보기
54. Kucukcakar, Kayhan; Helaihel, Rachid N., System and method for optimizing exceptions.

    상세보기
55. Bowen, Matt, System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures.

    상세보기
56. Betz, Vaughn; Ahmed, Elias; Neto, David, Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements.

    상세보기
57. Beausang James (Mountain View CA) Walker Robert (Boulder CO), Test ready compiler for design for test synthesis.

    상세보기
58. Beausang James ; Walker Robert, Test ready compiler for design for test synthesis.

    상세보기
59. Frankle Jon A. (San Jose CA) Chene Mon-Ren (Cupertino CA), Timing driven method for laying out a user\s circuit onto a programmable integrated circuit device.

    상세보기
60. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Kim, Henry; Pedersen, Bruce; Wysocki, Chris; Lane, Christopher F.; Marquardt, Alexander; Santurkar, Vikram; Betz, Vaughn, Versatile logic element and logic array block.

    상세보기
61. Mahajan Shekhar Y. ; Shao Wenyi, Virtual programmable device and method of programming.

    상세보기
더보기