Locked-loop quiescence apparatus, systems, and methods
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03L-007/06
H03L-007/081
H03L-007/087
H03L-007/091
H03L-007/095
G11C-011/4063
출원번호
US-0305953
(2014-06-16)
등록번호
US-9444469
(2016-09-13)
발명자
/ 주소
Becker, Eric
Roth, Brandon
Schafer, Scott
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Schwegman Lundberg & Woessner, P.A.
인용정보
피인용 횟수 :
0인용 특허 :
10
초록▼
Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to pr
Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.
대표청구항▼
1. An apparatus comprising: a variable delay line;a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line;a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay
1. An apparatus comprising: a variable delay line;a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line;a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay line input clock signal to an edge position associated with a delayed version of a clock signal fed back to the primary phase detector from an output of the variable delay line and to provide at least one phase difference signal to the delay control module, the phase difference signal to cause the delay control module to select the amount of delay such that a selected phase relationship is maintained between the variable delay line input clock signal and the clock signal fed back to the primary phase detector from the output of the variable delay line, the variable delay line, the delay control module, and the primary phase detector to interoperate as a delay locked loop (DLL);a quiescence control module to break every feedback loop associated with the variable delay line in the DLL in a quiescence mode to cause the DLL to be in an open-loop operation and to prevent updates to the variable delay line in the quiescence mode; anda lock indicator output at the quiescence enable module to provide an indication that the DLL has been quiesced and/or locked. 2. The apparatus of claim 1, wherein the quiescence control module further comprises: a quiescence disable module to disable DLL quiescent-mode operation upon command and/or in response to a sensed condition. 3. The apparatus of claim 1, further comprising: a clock counter associated with the quiescence control module to count clock cycles following initialization of the DLL and to enable the quiescence control module to initiate quiescence operations after a selected number of clock cycles have occurred. 4. The apparatus of claim 1, further comprising: a timer associated with the quiescence control module to enable the quiescence control module to initiate quiescence operations after a selected period of time has elapsed following initialization of the DLL. 5. The apparatus of claim 1, wherein the DLL comprises a low-power duty cycle corrector (DCC). 6. An apparatus comprising: a variable delay line;a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line;a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay line input clock signal to an edge position associated with a delayed version of a clock signal fed back to the primary phase detector from an output of the variable delay line and to provide at least one phase difference signal to the delay control module, the phase difference signal to cause the delay control module to select the amount of delay such that a selected phase relationship is maintained between the variable delay line input clock signal and the clock signal fed back to the primary phase detector from the output of the variable delay line, the variable delay line, the delay control module, and the primary phase detector to interoperate as a delay locked loop (DLL);at least one of a first circuit coupled to the delay control module to interrupt the delay control module output, a second circuit coupled to the primary phase detector to interrupt the variable delay line input clock signal, or a third circuit coupled to the primary phase detector to interrupt the clock signal fed back to the primary phase detector from the output of the variable delay line;a quiescence control module to break every feedback loop associated with the variable delay line in the DLL in a quiescence mode to cause the DLL to be in an open-loop operation and to prevent updates to the variable delay line in the quiescence mode, wherein the quiescence control module further comprises a quiescence enable module coupled to at least one of the first circuit, the second circuit, or the third circuit to open a first switch, a second switch, or a third switch to break the feedback loop associated with the DLL, and a quiescence enable input to the quiescence enable module to receive a quiescence enable signal as a command to initiate DLL quiescence operations; anda lock indicator output at the quiescence enable module to provide an indication that the DLL has been quiesced and/or locked. 7. An apparatus comprising: a variable delay line;a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line;a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay line input clock signal to an edge position associated with a delayed version of a clock signal fed back to the primary phase detector from an output of the variable delay line and to provide at least one phase difference signal to the delay control module, the phase difference signal to cause the delay control module to select the amount of delay such that a selected phase relationship is maintained between the variable delay line input clock signal and the clock signal fed back to the primary phase detector from the output of the variable delay line, the variable delay line, the delay control module, and the primary phase detector to interoperate as a delay locked loop (DLL);a quiescence control module to break every feedback loop associated with the variable delay line in the DLL in a quiescence mode to cause the DLL to be in an open-loop operation and to prevent updates to the variable delay line in the quiescence mode; anda lock-indicating phase detector coupled to the quiescence control module, the lock-indicating phase detector having a wider hysteresis curve than the primary phase detector, the lock-indicating phase detector to compare the edge position associated with the variable delay line input clock signal to the edge position associated with a delayed version of a clock signal fed back to the lock-indicating phase detector from an output of the variable delay line and to provide a signal to enable the quiescence control module to initiate quiescence operations at least partially in response to the lock-indicating phase detector reaching a phase-equal state. 8. An apparatus comprising: a variable delay line;a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line;a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay line input clock signal to an edge position associated with a delayed version of a clock signal fed back to the primary phase detector from an output of the variable delay line and to provide at least one phase difference signal to the delay control module, the phase difference signal to cause the delay control module to select the amount of delay such that a selected phase relationship is maintained between the variable delay line input clock signal and the clock signal fed back to the primary phase detector from the output of the variable delay line, the variable delay line, the delay control module, and the primary phase detector to interoperate as a delay locked loop (DLL);a quiescence control module to break every feedback loop associated with the variable delay line in the DLL in a quiescence mode to cause the DLL to be in an open-loop operation and to prevent updates to the variable delay line in the quiescence mode; anda lock-indicating filter coupled to the primary phase detector to monitor the phase difference signal and to enable the quiescence control module to initiate quiescence operations at least partially in response to a selected series of transitions of the phase difference signal indicating that the DLL has achieved a locked state. 9. A delay locked loop (DLL) comprising: a variable delay line to receive an input clock signal and provide an output clock signal at an output of the variable delay line;a phase detector to generate an output signal based on the input clock signal and a signal generated from a feedback loop coupled to the output of the of the variable delay line;a delay control module to select an amount of delay provided by the variable delay line based on the output signal from the phase detector; and a control module to initiate a quiescence mode to cause the DLL to be in an open-loop operation and to prevent updates to the variable delay line in the quiescence mode from every feedback loop associated with the variable delay line, wherein the control module is configured to break the feedback loop based on output from a temperature sensor. 10. A delay locked loop (DLL) comprising: a variable delay line to receive an input clock signal and provide an output clock signal;a phase detector to generate an output signal based on the input clock signal and a signal generated based on the output clock signal;a delay control module to select an amount of delay provided by the variable delay line based on the output signal from the phase detector; anda control module to initiate a quiescence mode to cause the DLL to be in an open-loop operation, the control module includes inputs to receive an operating temperature level from a temperature sensor to disable the quiescence mode based on operating temperature level from the temperature sensor reaching a threshold level in order to cause the DLL to be in a close-loop mode of the DLL. 11. The DLL of claim 10, wherein the control module is configured to disable the quiescence mode based on the operating temperature reaching a threshold level. 12. The DLL of claim 10, wherein the control module is configured to initiate the quiescence mode based an amount of time that has elapsed following initialization of the DLL. 13. The DLL of claim 10, wherein the control module is configured to initiate the quiescence mode based on a number of clock cycles that has occurred after initialization of the DLL. 14. A delay locked loop (DLL) comprising: a variable delay line to receive an input clock signal and provide an output clock signal;a phase detector to generate an output signal based on the input clock signal and a signal generated based on the output clock signal;a delay control module to select an amount of delay provided by the variable delay line based on the output signal from the phase detector; anda control module including inputs to receive an operating temperature level from a temperature sensor to decide whether to transition the DLL to or from a quiescent-mode operation based on the operating temperature level from the temperature sensor. 15. The DLL of claim 14, wherein the control module is configured to determine whether the operating temperature level from the temperature sensor has reached a threshold beyond which quiescence-mode operation causes data errors. 16. The DLL of claim 15, wherein the control module is configured generate a quiescence-mode turn-off event if the operating temperature level from the temperature sensor has reached the threshold beyond which the quiescence-mode operation causes data errors.
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