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A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional bl

A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

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1. A chip arrangement for use in processing communication signals with an electrified computing device, the communication signals being processed in accordance with any one of a plurality of communication protocols, each communication protocol being defined as a series of algorithms, the chip arrang

1. A chip arrangement for use in processing communication signals with an electrified computing device, the communication signals being processed in accordance with any one of a plurality of communication protocols, each communication protocol being defined as a series of algorithms, the chip arrangement comprising: a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols, wherein at least some of the same megafunctions are used with two or more communication protocols, and wherein each of the chip arrangement and a central processing unit, external to the chip arrangement, implements lower layers of each of the communication protocols;a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the communication protocols;wherein at least some of the megafunctions are parameterized, the parameters of at least some of the parameterized megafunctions are adapted to be dynamically changed, based on data stored in a memory external to the chip arrangement and accessible to the chip arrangement via an input/output block, in response to determination and as a function of the communication protocol of the communication signals being processed;buses interconnecting the megafunctions; andan analyzer configured so as to determine the communication protocol of the signal processed by the chip arrangement, and apply the necessary control signals so as to automatically configure the switches and interconnect the necessary megafunctions for processing the communication signals according to the determined protocol, wherein the protocol for processing of the communication signals is determined by a hand-off protocol between communication standards; andwherein the size of at least one of the buses is adapted to be dynamically changed depending on the determined communication protocol of the communication signals. 2. The chip arrangement according to claim 1, wherein the control signals for changing parameters of the parameterized megafunctions are stored in memory. 3. The chip arrangement according to claim 1, wherein the control signals for changing the parameters of the parameterized megafunctions are inserted on-line from outside the chip architecture. 4. The chip arrangement according to claim 1, wherein the control signals are stored in memory. 5. The chip arrangement according to claim 1, wherein the control signals are inserted on-line from outside the chip architecture. 6. The chip arrangement according to claim 5, further including an interconnect network among the megafunctions, and memory for storing a set of signals for reconfiguring the megafunctions and interconnect network between the megafunctions so as to set the parameters and algorithms associated with the protocol of the signals being processed. 7. The chip arrangement according to claim 5, wherein the analyzer is an algorithm performed by the system architecture. 8. The chip arrangement according to claim 7, wherein the analyzer is an algorithm for checking the strength of the signals processed by the chip architecture. 9. The chip arrangement according to claim 5, wherein the analyzer is responsive to the user input to the system architecture. 10. The chip arrangement according to claim 5, further including a control for sensing the protocol of the signal, and operating the switches and configuring the megafunctions accordingly. 11. The chip arrangement according to claim 5, wherein the protocol for processing of the signal is determined by a hand-off protocol between communication standards. 12. The chip arrangement according to claim 5, wherein at least one protocol implements the same algorithm at different stages of the protocol, as a function of a change in the receipt/transmission conditions. 13. The chip arrangement according to claim 5, wherein at least one protocol implements the same algorithm at different megafunctions of the same stage of the protocol as a function of a change in the receipt/transmission conditions. 14. A chip arrangement for use in processing communication signals encoded in an electrified computing device, wherein the communication signals are processed in accordance with any one of a plurality of selected communication protocols, each communication protocol being defined as a series of algorithms, the chip arrangement comprising: all of the algorithms necessary to implement the plurality of selected communication protocols, at least some of the algorithms being partitioned so as to define a plurality of domains of the same or similar algorithms commonly used by more than one of the selected communication protocols, wherein the domains associated with each communication protocol are arranged so that they can be implemented in a manner so as to define a set of parametrized megafunctions comprising a plurality of functional blocks configured to implement the physical layer of the corresponding selected communication protocol, wherein each of the chip arrangement and a central processing unit, external to the chip arrangement, implements lower layers of each of the communication protocols, and wherein parameters of at least some of the parameterized megafunctions are adapted to be dynamically changed, based on data stored in a memory external to the chip arrangement and accessible to the chip arrangement via an input/output block;a plurality of switches and buses configured to selectively interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; andan analyzer configured so as to determine the communication protocol of the signal processed by the chip arrangement in accordance with any one of a number of known communication protocols and with at least one hand-off communication protocol used to dynamically change between at least two known communication protocols, and apply control signals as a function of the determined communication protocol for automatically configuring the chip arrangement to interconnect the necessary megafunctions for processing the communications according to the determined communication protocol, wherein the size of at least one of the buses is adapted to be dynamically changed depending on the determined communication protocol of the communication signals. 15. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving orthogonal transforms of said signals. 16. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving cosine and sine transforms. 17. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving Hilbert transforms. 18. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving Walsh functions. 19. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving Fourier transforms. 20. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement algorithms involving Walsh-Hadamard transforms. 21. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to perform processing of trellises defining the signals. 22. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a search of the minimum/maximum weight path, the BCJR algorithm for calculation of a MAP, and a belief propagation algorithm. 23. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement matrix-vector operations. 24. The chip arrangement according to claim 23, wherein one or more of the megafunctions is configured to implement matrix-vector operations in finite and/or infinite fields. 25. The chip arrangement according to claim 23, wherein one or more of the megafunctions is configured to implement additional operations supported by the matrix-vector operations including polynomial convolutions and vector coordinate permutations. 26. The chip arrangement according to claim 14, wherein at least one or more of the megafunctions is configured to implement a process including multiplication of matrices by vectors, scalar product of vectors, and interleaving. 27. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of decoding convolution codes. 28. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of decoding turbo codes. 29. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of decoding low density parity check (LDPC) codes. 30. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of decoding algebraic codes. 31. The chip arrangement according to claim 14, wherein the algebraic codes include Reed-Solomon codes. 32. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of equalization of the processed signals. 33. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of synchronizing the processed signals. 34. The chip arrangement according to claim 14, wherein at least one protocol implements a space-time coding/decoding function. 35. The chip arrangement according to claim 14, wherein one or more of the megafunctions is configured to implement a process of MIMO processing of the processed signals. 36. A chip arrangement for use in processing communication signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms in an electrified computing device, comprising: an input/output for receiving input data and providing output processed data;a memory including a listing of all algorithms necessary to implement all of the selected communication protocols; at least some of the algorithms being partitioned so as to define domains, each of the same or similar algorithms used by one or more of the communication protocols and arranged so that they can be implemented in a manner so as to define a unique set of megafunctions comprising a unique plurality of reusable, reconfigurable functions blocks for each communication protocol and used to implement the physical layer of the corresponding selected protocol, wherein each of the chip arrangement and a central processing unit (CPU), external to the chip arrangement, implements lower layers of each of the communication protocols;a plurality of switches configured and responsive to control signals so as to interconnect the megafunctions in each of the plurality of configurations as determined by the communication protocol of the encoded signals;a reconfigurable net bus for interconnecting the switches, megafunctions and input/output; andan analyzer configured so as to determine the communication protocol of the signal processed by the chip arrangement, and apply the necessary control signals so as to automatically configure the switches and interconnect the necessary megafunctions for processing the communication signals according to the determined protocol, wherein the protocol for processing of the communication signals is determined by a hand-off protocol between communication standards, and wherein the size of the net bus is adapted to be dynamically changed depending on the determined communication protocol of the communication signals;wherein the CPU is external to the chip arrangement and is configured to control the configuration of the megafunctions, switches and buses as a function of the communication protocol of the encoded signals; andwherein at least some of the megafunctions are parameterized megafunctions, the parameters of at least some of the parameterized megafunctions being adapted to dynamically change, based on data stored in a memory external to the chip arrangement and accessible to the chip arrangement via an input/output block, in response to determination and a function of the communication protocol of the communication signal being processed. 37. The chip arrangement according to claim 36, wherein at least some of the megafunctions include reconfigurable parameters, and the CPU is configured to control the configuration of the megafunctions, switches and net bus including dynamic control of the reconfigurable parameters. 38. The chip arrangement according to claim 37, wherein the memory includes RAM configured to store compiled software instructions. 39. The chip arrangement according to claim 37, further including a variable clock applied to different megafunctions and configured to allow parallel processing of data at different clocking rates. 40. The chip arrangement according to claim 36, wherein the CPU includes a processor configured to implement higher layer protocols. 41. The chip arrangement according to claim 36, further including an enabler for applying a periodic enabling signal to different ones of the megafunctions. 42. An electrified computing device for use in processing communication signals processed in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising: an antenna for receiving and transmitting a signal encoded in accordance with anyone of a plurality of communication protocols;a baseband processor for processing the signals received and transmitted by the antenna;a chip arrangement comprising: all of the algorithms necessary to implement all of the communication protocols, at least some of the algorithms being commonly used by at least two of the communication protocols and being partitioned so as define a set of megafunctions comprising a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols, wherein each of the chip arrangement and a central processing unit, external to the chip arrangement, implements lower layers of each of the communication protocols;a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;wherein at least some of the same megafunctions are parameterized, the parameters of at least some of the parameterized megafunctions are adapted to be dynamically changed, based on data stored in a memory external to the chip arrangement and accessible to the chip arrangement via an input/output block, in response to determination and a function of the communication protocol of the communication signals being processed, the communication protocol being any one of a number of known communication protocols and at least one hand-off protocol used to dynamically change between at least two known communication protocols;buses interconnecting the megafunctions; andan analyzer configured so as to determine the communication protocol of the signal processed by the chip architecture, and apply the necessary control signals so as to automatically configure the switches and interconnect the necessary megafunctions for processing the communication signals according to the determined protocol, wherein the protocol for processing of the communication signals is determined by a hand-off protocol between communication standards;wherein the size of at least one of the buses is adapted to be dynamically changed depending on the determined communication protocol of the communication signals. 43. The computing device according to claim 42, wherein the computing device includes a transmitter, and the baseband processor encodes the processed signal in accordance with any one of said protocols prior to transmitting the signal. 44. The computing device according to claim 42, wherein the computing device includes a receiver, and the baseband processor decodes the processed signal in accordance with any one of said protocols after receiving the processed signal. 45. The computing device according to claim 42, wherein the computing device is adapted to transmit and receive, and the baseband processor is configured to encode the processed signal in accordance with any one of the protocols prior to transmitting an encoded signal, and decode the processed signal in accordance with any one of said protocols after receiving the processed signal.