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Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master gl

Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

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1. An apparatus, comprising: an interconnect;a plurality of components each comprising a configuration memory and each coupled to the interconnect, wherein the configuration memory of each component is allocated a unique address space on the interconnect, wherein a global configuration portion of th

1. An apparatus, comprising: an interconnect;a plurality of components each comprising a configuration memory and each coupled to the interconnect, wherein the configuration memory of each component is allocated a unique address space on the interconnect, wherein a global configuration portion of the configuration memory of each component is allocated to global configuration information common to the plurality of components, and wherein the global configuration portion of the configuration memory of one of the plurality of components is designated as a master global configuration for the plurality of components; anda configuration module coupled to the interconnect and configured to: receive a request from a configuration source;detect that the request is a write request to the master global configuration for the plurality of components;in response to said detecting, broadcast the write request to the global configuration portion of the configuration memory of each of the plurality of components via the interconnect;receive another request from the configuration source; andin response to determining that the other request is a write request to the global configuration portion of the configuration memory of a particular one of the components that is not designated as the master global configuration for the plurality of components, send the write request only to the particular component via the interconnect. 2. The apparatus as recited in claim 1, wherein the broadcasted write request updates global configuration information in the global configuration portion of the configuration memory of each of the plurality of components. 3. The apparatus as recited in claim 1, wherein the configuration memory of each component comprises one or more programmable registers, and wherein the interconnect is a bus subsystem. 4. The apparatus as recited in claim 1, wherein the configuration source is a processor coupled to the configuration module and configured to control global configuration of the plurality of components. 5. The apparatus as recited in claim 1, wherein, to detect that the request is a write request to the master global configuration for the plurality of components, the configuration module is configured to decode address information for the request to determine that the request is targeted at the global configuration portion of the configuration memory of the component that is designated as the master global configuration for the plurality of components. 6. The apparatus as recited in claim 1, wherein, to broadcast the write request to the global configuration portion of the configuration memory of each of the plurality of components via the interconnect, the configuration module is configured to: translate address information for the request to determine an interconnect address within the address space of the configuration memory of each of the plurality of components; andsend the write request to each of the plurality of components via the interconnect according to the determined interconnect addresses. 7. The apparatus as recited in claim 1, wherein the component that is designated as the master global configuration for the plurality of components is a component that only serves as the master global configuration for the other components, wherein the other components are functional components that each perform an operation of the apparatus according to global configuration information in the global configuration portion of the configuration memory of the respective component. 8. A method, comprising: designating one of a plurality of components coupled to an interconnect as a master global configuration component for all of the plurality of components;receiving, by a module coupled to the interconnect, a write request directed to the master global configuration component;in response to said receiving, broadcasting the write request to each of the plurality of components via the interconnect;in response to the broadcasted write request directed to the master global configuration component, updating global configuration information in a global configuration portion of a configuration memory of each of the plurality of components;receiving, by the module, another write request from the configuration source; andin response to determining that the other request is a write request to a particular one of the components that is not designated as the master global configuration component, sending the other write request only to the particular component via the interconnect. 9. The method as recited in claim 8, wherein each of the plurality of components comprises a configuration memory, wherein the configuration memory of each component is allocated a unique address space on the interconnect, wherein a global configuration portion of the configuration memory of each component is allocated to global configuration information common to the plurality of components. 10. The method as recited in claim 8, wherein the configuration memory of each component comprises one or more programmable registers, wherein the interconnect is a bus subsystem, and wherein the configuration source is a processor coupled to the module and configured to control global configuration of the plurality of components. 11. The method as recited in claim 8, further comprising decoding, by the module, address information for the write request to determine that the request is targeted at a global configuration portion of a configuration memory of the component that is designated as the master global configuration for the plurality of components. 12. The method as recited in claim 8, wherein said broadcasting the write request to each of the plurality of components via the interconnect comprises: translating address information for the request to determine an interconnect address within the address space of the configuration memory of each of the plurality of components; andsending the write request to each of the plurality of components via the interconnect according to the determined interconnect addresses. 13. The method as recited in claim 8, further comprising: receiving, by the module, another write request directed to one of the components that is not designated as the master global configuration component for the plurality of components;in response to said receiving the other write request, broadcasting the other write request to each of the plurality of components via the interconnect; andin response to the broadcasted other write request, decoding, by each of the plurality of components, address information for the other write request to determine if the other write request is targeted at the configuration memory of the respective component, wherein the write request is accepted by the component only if targeted at the configuration memory of the component. 14. An apparatus, comprising: an interconnect;a block processing pipeline that includes a plurality of functional components, each functional component coupled to the interconnect and configured to perform one or more operations on a block of pixels from a frame passing through the pipeline;wherein a configuration memory of each functional component of the pipeline is allocated a unique address space on the interconnect, wherein a global configuration portion of the configuration memory of each functional component in the pipeline is allocated to global configuration information common to the functional components of the pipeline, and wherein the global configuration portion of the configuration memory of one of the plurality of functional components in the pipeline is designated as a master global configuration for the pipeline;a configuration module coupled to the interconnect and configured to: receive a request from a pipeline configuration source;determine that the request is a write request to the master global configuration for the pipeline; andin response to said determining, broadcast the write request to the global configuration portion of the configuration memory of each of the plurality of functional components of the pipeline via the interconnect, wherein the broadcasted write request updates global configuration information in the global configuration portion of the configuration memory of each of the plurality of functional components of the pipeline;receive another request from the configuration source; andin response to determining that the other request is a write request to the global configuration portion of the configuration memory of a particular one of the functional components that is not designated as the master global configuration for the pipeline, send the write request only to the particular functional component via the interconnect. 15. The apparatus as recited in claim 14, wherein the apparatus further comprises at least one processor, and wherein the configuration source is a software program executing on the at least one processor. 16. The apparatus as recited in claim 14, wherein, to determine that the request is a write request to the master global configuration for the pipeline, the configuration module decodes address information for the request to determine that the request is targeted at the global configuration portion of the configuration memory of the functional component that is designated as the master global configuration for the pipeline. 17. The apparatus as recited in claim 14, wherein, to broadcast the write request to the global configuration portion of the configuration memory of each of the plurality of functional components of the pipeline via the interconnect, the configuration module is configured to: translate address information for the request to determine an interconnect address within the address space of the configuration memory of each of the plurality of functional components; andsend the write request to each of the plurality of functional components via the interconnect according to the determined interconnect addresses.