Methods for semiconductor sensor structures with reduced dislocation defect densities
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/00
H01L-027/146
H01L-027/144
H01L-031/0304
H01L-031/0312
H01L-031/103
H01L-031/105
H01L-021/02
H01L-021/762
출원번호
US-0755665
(2015-06-30)
등록번호
US-9455299
(2016-09-27)
발명자
/ 주소
Cheng, Zhiyuan
Fiorenza, James
Sheen, Calvin
Lochtefeld, Anthony J.
출원인 / 주소
Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
Slater Matsil, LLP
인용정보
피인용 횟수 :
0인용 특허 :
259
초록▼
Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing dev
Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
대표청구항▼
1. A method comprising: converting received light into a voltage signal by a sensor, the sensor being disposed in a first crystalline material, the first crystalline material being in a recess in a substrate, the recess having non-crystalline sidewalls, the substrate comprising a second crystalline
1. A method comprising: converting received light into a voltage signal by a sensor, the sensor being disposed in a first crystalline material, the first crystalline material being in a recess in a substrate, the recess having non-crystalline sidewalls, the substrate comprising a second crystalline material lattice mismatched to the first crystalline material; andamplifying the voltage signal into an amplified signal using a first transistor, the first transistor comprising a first source/drain region disposed in the second crystalline material. 2. The method of claim 1, wherein the sensor comprises a p-n junction in the first crystalline material. 3. The method of claim 1, wherein the sensor comprises a p-i-n structure in the first crystalline material. 4. The method of claim 1 further comprising reading out the amplified signal comprising selectively applying a column signal to a second transistor and a row signal to a third transistor, the second transistor having a second source/drain region disposed in the second crystalline material, the third transistor having a third source/drain region disposed in the second crystalline material. 5. The method of claim 1, wherein a dielectric material is disposed along a bottom surface of the recess, an opening being defined through the dielectric material to the bottom surface of the recess, the first crystalline material being disposed at least partially in the opening. 6. The method of claim 1, wherein a dielectric material is disposed along a bottom surface of the recess, a plurality of openings being defined through the dielectric material to the bottom surface of the recess, the first crystalline material being disposed at least partially in each of the plurality of openings. 7. The method of claim 1, wherein the first crystalline material comprises defects arising from lattice-mismatch to the second crystalline material, a majority of the defects being trapped at the non-crystalline sidewalls. 8. The method of claim 1, wherein a graded buffer material is disposed in the recess, the first crystalline material being disposed on the graded buffer material. 9. A method comprising: forming a recess in a first crystalline material of a substrate;forming a first non-crystalline material along sidewalls of the recess;epitaxially growing a second crystalline material in the recess, the second crystalline material being lattice mismatched to the first crystalline material, the second crystalline material comprising defects arising from the lattice-mismatch to the first crystalline material in a lower portion of the recess, the second crystalline material in an upper portion of the recess being substantially free from defects;forming a photodetector in the second crystalline material; andforming a transistor at least partially in the first crystalline material. 10. The method of claim 9, wherein the photodetector comprises a lateral p-n junction in the second crystalline material. 11. The method of claim 9, wherein the photodetector comprises a lateral p-i-n structure in the second crystalline material. 12. The method of claim 9 further comprising: forming a second non-crystalline material along a bottom surface of the recess; anddefining an opening through the second non-crystalline material to the bottom surface of the recess, the second crystalline material being disposed at least partially in the opening. 13. The method of claim 9 further comprising: forming a second non-crystalline material along a bottom surface of the recess; anddefining a plurality of openings through the second non-crystalline material to the bottom surface of the recess, the second crystalline material being disposed at least partially in each of the plurality of openings and coalescing over the first non-crystalline material. 14. The method of claim 9 further comprising forming a graded buffer material in the recess, the second crystalline material being formed on the graded buffer material. 15. The method of claim 9, wherein a topmost surface of the photodetector extends above a topmost surface of the first crystalline material of the substrate. 16. A method comprising: forming a trench with non-crystalline sidewalls on a first crystalline material of a substrate;epitaxially growing a second crystalline material lattice mismatched to the first crystalline material in the trench, a lower portion of the second crystalline material in the trench having defects arising from the lattice mismatch to the first crystalline material, an upper portion of the second crystalline material in the trench being substantially free from defects arising from the lattice mismatch;forming a p-region in the upper portion of the second crystalline material, the p-region extending from an upper surface of the second crystalline material into the second crystalline material; andforming an n-region in the upper portion of the second crystalline material, the n-region extending from the upper surface of the second crystalline material into the second crystalline material. 17. The method of claim 16, wherein an intrinsic region of the second crystalline material is disposed between the p-region and the n-region. 18. The method of claim 16 further comprising: forming a first contact to the p-region, the first contact being on the upper surface of the second crystalline material; andforming a second contact to the n-region, the first contact being on the upper surface of the second crystalline material. 19. The method of claim 16, wherein the trench is formed in a non-crystalline layer over the substrate. 20. The method of claim 16, wherein the trench is formed in the first crystalline material of the substrate, a non-crystalline material being formed along sidewalls of the trench to form the non-crystalline sidewalls.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (259)
Nakahata, Seiji; Hirota, Ryu; Motoki, Kensaku; Okahisa, Takuji; Uematsu, Kouji, A1InGaN mixture crystal substrate, method of growing same and method of producing same.
Mirabedini,Mohammad R.; Sukharev,Valeriy, Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide.
Bean John C. (New Providence NJ) Higashi Gregg S. (Basking Ridge NJ) Hull Robert (South Orange NJ) Peticolas Justin L. (Wescosville PA), Article comprising a lattice-mismatched semiconductor heterostructure.
Imer,Bilge M.; Speck,James S.; DenBaars,Steven P., Defect reduction of non-polar and semi-polar III-Nitrides with sidewall lateral epitaxial overgrowth (SLEO).
Kulkarni Shriram ; Mazumder Pinaki ; Haddad George I., Digital logic design using negative differential resistance diodes and field-effect transistors.
Vangieson Edward A. (Lawrenceville NJ) York Pamela K. (Trenton NJ) Connolly John C. (Monmouth Junction NJ), Distributed feedback-channeled substrate planar semiconductor laser.
Shih-Yuan Wang ; Changhua Chen ; Yong Chen ; Scott W. Corzine ; R. Scott Kern ; Richard P. Schneider, Jr., Epitaxial material grown laterally within a trench and method for producing same.
Usui Akira,JPX ; Sakai Akira,JPX ; Sunakawa Haruo,JPX ; Mizuta Masashi,JPX ; Matsumoto Yoshishige,JPX, GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor.
Weichold Mark H. (College Station TX) Kinard William B. (Bryan TX) Kirk Wiley P. (College Station TX), Gate adjusted resonant tunnel diode device and method of manufacture.
Naoki Shibata JP; Jun Ito JP; Toshiaki Chiyo JP; Shizuyo Asami JP; Hiroshi Watanabe JP; Shinya Asami JP, Group III nitride compound semiconductor device and method for producing.
Shibata,Naoki; Ito,Jun; Chiyo,Toshiaki; Asami,Shizuyo; Watanabe,Hiroshi; Asami,Shinya, Group III nitride compound semiconductor device and method for producing the same.
Kuramoto, Masaru; Sunakawa, Haruo, Group III-V compound semiconductor crystal structure and method of epitaxial growth of the same as well as semiconductor device including the same.
Iles, Peter A.; Ho, Frank F.; Yeh, Yea-Chuan M., High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same.
Ohkubo Yoshiyuki,JPX ; Nishizaka Kan,TRX, Information recording medium, method for manufacturing the medium, and apparatus for manufacturing the medium.
Demeester Piet M. (Gent BEX) Ackaert Ann M. (Gent BEX) Van Daele Peter P. (Aalst BEX) Lootens Dirk U. (Deinze BEX), Integration of GaAs on Si substrates.
Morita, Etsuo, METHOD OF MANUFACTURING CRYSTAL OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, CRYSTAL SUBSTRATE OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, CRYSTAL FILM OF III-V COMPOUNDS OF THE NITRIDE SYSTEM, AND METHOD.
Wu Albert T. (San Jose CA) Nozaki Shinji (Tokyo CA JPX) George Thomas (Albany CA) Lee Sandra S. (Los Altos CA) Umeno Masayoshi (Nagoya JPX), Masking technique for depositing gallium arsenide on silicon.
Pham, Daniel T.; Barr, Alexander L.; Mathew, Leo; Nguyen, Bich-Yen; Vandooren, Anne M.; White, Ted R., Method for forming a double-gated semiconductor device.
Bich-Yen Nguyen ; William J. Taylor, Jr. ; Philip J. Tobin ; David L. O'Meara ; Percy V. Gilbert ; Yeong-Jyh T. Lii ; Victor S. Wang, Method for forming a semiconductor device with an opening in a dielectric layer.
Buynoski, Matthew S.; Dakshina-Murthy, Srikanteswara; Tabery, Cyrus E.; Wang, Haihong; Yang, Chih-Yuh; Yu, Bin, Method for forming fins in a FinFET device using sacrificial carbon layer.
Koike, Masayoshi; Nagai, Seiji, Method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor.
Meister Thomas (Taufkirchen DEX) Stengl Reinhard (Stadtbergen DEX), Method for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for man.
Fitzgerald ; Jr. Eugene A. (Ithaca NY) Ast Dieter G. (Ithaca NY), Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers.
Fitzgerald ; Jr. Eugene A. (Ithaca NY) Ast Dieter G. (Ithaca NY), Method for reducing or eliminating interface defects in mismatched semiconductor epilayers.
Djomehri, Ihsan J.; Goo, Jung-Suk; Krishnan, Srinath; Maszara, Witold P.; Pan, James N.; Xiang, Qi, Method of growing as a channel region to reduce source/drain junction capacitance.
Van der Wagt Jan Paul ; Wilk Glen D. ; Wallace Robert M., Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Method of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substr.
Mosher Dan M. (Plano TX) Blanton Cornelia H. (Plano TX) Trogolo Joe R. (Plano TX) Latham Larry (Garland TX) Cotton David R. (Plano TX), Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices.
Singh,Jagar; Hou,Yong Tian; Li,Ming Fu, Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration.
Pankove Jacques I. (Princeton NJ) Wu Chung P. (Trenton NJ), Method of making selective crystalline silicon regions containing entrapped hydrogen by laser treatment.
Thomas, III, Stephen; Elliot, Ken; Chow, Dave, Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom.
Yacobi Ben G. (Natick MA) Zemon Stanley (Brookline MA) Jagannath Chirravuri (Needham MA), Method of manufacturing an heteroepitaxial semiconductor structure.
Koh Risho (Tokyo JPX) Ogura Atsushi (Tokyo JPX), Method of producing a semiconductor on insulating substrate, and a method of forming a transistor thereon.
Kevin J. Linthicum ; Thomas Gehrke ; Robert F. Davis, Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
Macdonald Perry A. (Culver City CA) Larson Lawrence E. (Bethesda MD) Case Michael G. (Thousand Oaks CA) Matloubian Mehran (Encino CA) Chen Mary Y. (Agoura CA) Rensch David B. (Thousand Oaks CA), Monolithic microwave integrated circuit and method.
Paton, Eric N.; Xiang, Qi; Besser, Paul R.; Lin, Ming-Ren; Ngo, Minh V.; Wang, Haihong, Mosfets incorporating nickel germanosilicided gate and methods for their formation.
Gehrke, Thomas; Linthicum, Kevin J.; Davis, Robert F., Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates.
Nishijima,Kazuki; Senda,Masanobu; Chiyo,Toshiaki; Ito,Jun; Shibata,Naoki; Hayashi,Toshimasa, Process for producing group III nitride compound semiconductor.
Nishida Shoji (Nagahama JPX) Yonehara Takao (Atsugi JPX), Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing.
Cavanaugh Marion E. (792 Paul Ave. Palo Alto CA 94306), Quantum field effect device with source extension region formed under a gate and between the source and drain regions.
Fan John C. C. (Chestnut Hill MA) Tsaur Bor-Yeu (Arlington MA) Gale Ronald P. (Bedford MA) Davis Frances M. (Framingham MA), Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth.
Simmons Jerry A. ; Sherwin Marc E. ; Drummond Timothy J. ; Weckwerth Mark V., Resonant tunneling device with two-dimensional quantum well emitter and base layers.
Salerno Jack P. (Waban MA) Lee Jhang W. (Mansfield MA) McCullough Richard E. (Wrentham MA), Selective OMCVD growth of compound semiconductor materials on silicon substrates.
Sasaki Kazuaki,JPX ; Yamamoto Osamu,JPX, Semiconductor light-emitting device capable of having good stability in fundamental mode of oscillation, decreasing curr.
Liu, Chun-Li; Barr, Alexander L.; Grant, John M.; Nguyen, Bich-Yen; Orlowski, Marius K.; Stephens, Tab A.; White, Ted R.; Thomas, Shawn G., Semiconductor structure with different lattice constant materials and method for forming the same.
Berger, Paul R.; Thompson, Phillip E.; Lake, Roger; Hobart, Karl; Rommel, Sean L., Si-based resonant interband tunneling diodes and method of making interband tunneling diodes.
Kapoor Ashok K. (Palo Alto CA) Ciacchella J. Frank (Sunnyvale CA), Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer.
Kong, Hua-Shuang; Edmond, John Adam; Haberern, Kevin Ward; Emerson, David Todd, Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures.
Kong, Hua-Shuang; Edmond, John Adam; Haberern, Kevin Ward; Emerson, David Todd, Single step pendeo-and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures.
Hosomi, Shigeyuki; Hisamatsu, Tadashi, Solar cell with bypass function and multi-junction stacked type solar cell with bypass function, and method for manufacturing these devices.
Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhi Yuan; Fiorenza, James, Solutions for integrated circuit integration of alternative active area materials.
Belyansky, Michael P.; Chidambarrao, Dureseti; Dokumaci, Omer H.; Doris, Bruce B.; Gluschenkov, Oleg, Structure and method to improve channel mobility by gate electrode stress modification.
Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
Freundlich Alexandre (Houston TX) Vilela Mauro F. (Houston TX) Bensaoula Abdelhak (Houston TX) Ignatiev Alex (Houston TX), Tandem solar cell with improved tunnel junction.
Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.