Method to co-integrate oppositely strained semiconductor devices on a same substrate
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/84
H01L-027/12
H01L-029/16
H01L-029/161
H01L-029/165
H01L-029/78
H01L-029/06
H01L-021/762
H01L-021/265
H01L-021/324
H01L-021/266
H01L-021/306
H01L-021/02
H01L-027/092
H01L-021/8238
출원번호
US-0955801
(2015-12-01)
등록번호
US-9460971
(2016-10-04)
발명자
/ 주소
Loubet, Nicolas
Maitrejean, Sylvain
Wacquez, Romain
출원인 / 주소
STMICROELECTRONICS, INC.
대리인 / 주소
Seed IP Law Group PLLC
인용정보
피인용 횟수 :
0인용 특허 :
5
초록▼
Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differentl
Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.
대표청구항▼
1. A method for forming differently strained regions of semiconductor on a substrate, the method comprising: forming a first semiconductor layer over a second semiconductor layer, wherein the first semiconductor layer forms under a first strain;implanting ions into a first region and not a second re
1. A method for forming differently strained regions of semiconductor on a substrate, the method comprising: forming a first semiconductor layer over a second semiconductor layer, wherein the first semiconductor layer forms under a first strain;implanting ions into a first region and not a second region of the second semiconductor layer, wherein the implanted ions amorphize the first region of the second semiconductor layer;recrystallizing the first region of the second semiconductor layer to form a second strain in the first region;removing the first semiconductor layer;forming a third semiconductor layer in contact with the second region and not in contact with the first region, wherein the third semiconductor layer is of a different chemical composition from the second semiconductor layer; andheating the substrate to condense a chemical component from the third semiconductor layer into the second region of the second semiconductor layer to form a third strain in the second region that is different from the second strain. 2. The method of claim 1, wherein the second semiconductor layer is disposed on an insulating layer. 3. The method of claim 2, wherein the insulating layer comprises an oxide or nitride having a thickness between about 5 nm and about 200 nm. 4. The method of claim 2, wherein the insulating layer is an ultrathin buried oxide layer. 5. The method of claim 1, wherein the second semiconductor layer has a thickness between approximately 5 nm and approximately 60 nm. 6. The method of claim 1, wherein the first semiconductor layer has a first lattice constant that differs from a second lattice constant of the second semiconductor layer. 7. The method of claim 6, wherein the first semiconductor layer comprises a SiGe or SiC layer and the second semiconductor layer comprises a Si layer. 8. The method of claim 1, further comprising doping the first or second region to be of a first conductivity type that is opposite a second conductivity type of the respective second or first region. 9. The method of claim 1, wherein the first and third strains are compressive strain and the second strain is tensile strain. 10. The method of claim 9, further comprising doping the first region to be of n-type conductivity or doping the second region to be of p-type conductivity. 11. The method of claim 1, wherein the first and third strains are tensile strain and the second strain is compressive strain. 12. The method of claim 1, wherein the third layer and first layer are formed of same chemical species. 13. The method of claim 12, wherein a concentration of the chemical species in the third layer differs from a concentration of the chemical species in the first layer. 14. The method of claim 13, wherein a concentration of a chemical species in the third layer before being condensed into the second region of the first layer is higher than a concentration of a same chemical species in the first layer. 15. The method of claim 1, further comprising forming the first semiconductor layer by epitaxial growth. 16. The method of claim 1, further comprising forming an ion blocking mask over the second region prior to implanting ions. 17. The method of claim 1, wherein recrystallizing comprises annealing the substrate at a temperature between about 500° C. and about 1100° C. 18. The method of claim 1, further comprising thinning the second semiconductor layer by an oxidation process after removing the first semiconductor layer. 19. The method of claim 1, wherein the second semiconductor layer is thinned to a thickness between approximately 5 nm and approximately 30 nm. 20. The method of claim 1, further comprising forming a mask over the first region prior to forming the third semiconductor layer, wherein the mask blocks the formation of the third semiconductor layer over the first region. 21. The method of claim 1, further comprising forming the third semiconductor layer by epitaxial growth. 22. The method of claim 1, wherein heating the substrate comprises oxidizing the third semiconductor layer. 23. The method of claim 1, further comprising: etching a trench through the second semiconductor layer between the first region and second region after heating the substrate; andfilling the trench with an insulating material. 24. The method of claim 1, further comprising: forming at least one n-channel FD-SOI FET in the first region; andforming at least one p-channel FD-SOI FET in the second region. 25. The method of claim 24, wherein a channel length of at least one PD-SOI PET is less than about 30 nm. 26. The method of claim 1, further comprising: forming at least one n-channel finFET in the first region; andforming at least one p-channel finFET in the second region. 27. The method of claim 26, wherein a fin width of at least one finFET is less than about 30 nm. 28. The method of claim 27, further comprising forming fins for the finFETs using a sidewall image transfer process. 29. A method for forming differently strained regions of semiconductor on a substrate, the method comprising: forming a first semiconductor layer over a second semiconductor layer, wherein the first semiconductor layer forms under a first strain;implanting ions into a first region and not a second region of the second semiconductor layer, wherein the implanted ions amorphize the first region of the second semiconductor layer and wherein the first region is immediately adjacent to the second region;recrystallizing the first region of the second semiconductor layer to form a second strain in the first region;thinning the second semiconductor layer after recrystallizing the first region; andheating the substrate to condense a chemical component into the second region of the second semiconductor layer to form a third strain in the second region that is different from the second strain. 30. The method of claim 29, further comprising forming a third semiconductor layer in contact with the second region and not in contact with the first region, wherein the third semiconductor layer has a chemical composition different than the second region. 31. The method of claim 30, further comprising: forming a trench through the second semiconductor layer between the first region and second region after implanting the ions; andfilling the trench with an insulating material. 32. The method of claim 29, wherein the second strain is of an opposite type than the third strain. 33. A method for forming differently strained regions of semiconductor on a substrate, the method comprising: forming a first semiconductor layer over a second semiconductor layer at a first area of the substrate, wherein the first semiconductor layer forms under a first strain;forming a third semiconductor layer over the second semiconductor layer at a second area of the substrate, wherein the third semiconductor layer forms under a second strain;implanting ions into a first region of the second semiconductor layer at the first area and into a second region of the second semiconductor layer at the second area, wherein the implanted ions amorphize the first region and second region of the second semiconductor layer; andrecrystallizing the first region and second region of the second semiconductor layer to form a third strain in the first region and a fourth strain in the second region. 34. The method of claim 33, further comprising: removing the first semiconductor layer and the third semiconductor layer; andremoving a portion of the second semiconductor layer so as to reduce the thickness of the second semiconductor layer at the first area and second area. 35. The method of claim 33, wherein the first area and second area are immediately adjacent. 36. The method of claim 35, further comprising: forming a trench through the second semiconductor layer between the first region and second region after implanting the ions; andfilling the trench with an insulating material. 37. The method of claim 33, further comprising doping the first region to be of n-type conductivity or doping the second region to be of p-type conductivity.
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이 특허에 인용된 특허 (5)
Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
Vasudev Prahalad K. (Santa Monica CA), Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and int.
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