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Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable ca

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

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1. An integrated circuit comprising: a variable capacitor array including a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, each of the plurality of variable capacitor cells having a capacitance configured to be controll

1. An integrated circuit comprising: a variable capacitor array including a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, each of the plurality of variable capacitor cells having a capacitance configured to be controlled independently of another of the plurality of variable capacitor cells, wherein a first variable capacitor cell of the plurality of variable capacitor cells includes: two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series and electrically connected to one another at a first intermediate node, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series and electrically connected to one another at a second intermediate node; anda first feed-forward capacitor electrically connected between the RF input and the first intermediate node to provide a feed-forward path from the RF input to the first intermediate node. 2. The integrated circuit of claim 1, wherein the first variable capacitor cell further comprises a second feed-forward capacitor electrically connected between the first intermediate node and the second intermediate node. 3. The integrated circuit of claim 2, wherein the first and second feed-forward capacitors provide at least one of voltage balancing, current balancing, or phase balancing to the two or more pairs of anti-series MOS capacitors. 4. The integrated circuit of claim 2, wherein the first feed-forward capacitor has a capacitance value that is greater than that of the second feed-forward capacitor. 5. The integrated circuit of claim 2, wherein the two or more pairs of anti-series MOS capacitors further comprises a third pair of anti-series MOS capacitors, wherein the third pair of anti-series MOS capacitors comprises a fifth MOS capacitor and a sixth MOS capacitor electrically connected in anti-series and electrically connected to one another at a third intermediate node, wherein the first variable capacitor cell further comprises a third feed-forward capacitor electrically connected between the second intermediate node and the third intermediate node. 6. The integrated circuit of claim 5, wherein the first feed-forward capacitor has a capacitance value that is greater than that of the second feed-forward capacitor, and wherein the second feed-forward capacitor has a capacitance value that is greater than that of the third feed-forward capacitor. 7. The integrated circuit of claim 1, wherein each of the plurality of variable capacitor cells comprises at least three pairs of anti-series MOS capacitors. 8. The integrated circuit of claim 1, further comprising a bias voltage generation circuit configured to bias the plurality of variable capacitor cells including the first variable capacitor cell to control a capacitance of the variable capacitor array. 9. The integrated circuit of claim 8, wherein the bias voltage generation circuit is configured to bias the first variable capacitor cell with a first bias voltage, wherein the bias voltage generation circuit is configured to control the first bias voltage to a voltage level selected from a discrete number of two or more bias voltage levels. 10. The integrated circuit of claim 9, wherein the first variable capacitor cell further comprises: a first control biasing resistor electrically connected between the first bias voltage and the first intermediate node; anda second control biasing resistor electrically connected between the first bias voltage and the second intermediate node. 11. The integrated circuit of claim 1, wherein the first variable capacitor cell further comprises: a first diode including an anode electrically connected to a body of the first MOS capacitor and a cathode electrically connected to a gate of the first MOS capacitor;a second diode including an anode electrically connected to a body of the second MOS capacitor and a cathode electrically connected to a gate of the second MOS capacitor;a third diode including an anode electrically connected to a body of the third MOS capacitor and a cathode electrically connected to a gate of the third MOS capacitor; anda fourth diode including an anode electrically connected to a body of the fourth MOS capacitor and a cathode electrically connected to a gate of the fourth MOS capacitor. 12. The integrated circuit of claim 1, wherein a gate of the first MOS capacitor is electrically connected to a gate of the second MOS capacitor at the first intermediate node, and wherein a gate of the third MOS capacitor is electrically connected to a gate of the fourth MOS capacitor at the second intermediate node. 13. The integrated circuit of claim 1, wherein a source and a drain of the first MOS capacitor are electrically connected to a source and a drain of the second MOS capacitor at the first intermediate node, and wherein a source and a drain of the third MOS capacitor are electrically connected to a source and a drain of the fourth MOS capacitor at the second intermediate node. 14. The integrated circuit of claim 1, wherein the integrated circuit does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array. 15. The integrated circuit of claim 1, wherein the integrated circuit is formed using a silicon on insulator (SOI) substrate. 16. A method of providing a variable capacitance in a radio frequency (RF) system, the method comprising: generating a plurality of bias voltages including a first bias voltage using a bias voltage generation circuit;controlling a voltage level of the first bias voltage based on a control signal using the bias voltage generation circuit;biasing a first variable capacitor cell of a plurality of variable capacitor cells in a variable capacitor array using the first bias voltage, the first bias voltage controlling a capacitance of the first variable capacitor cell independently of another of the plurality of variable capacitor cells, wherein the first variable capacitor cell includes two or more pairs of anti-series MOS capacitors electrically connected in series between a radio frequency (RF) input and an RF output of the variable capacitor array, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series and electrically connected to one another at a first intermediate node, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series and electrically connected to one another at a second intermediate node; andproviding a first feed-forward path from the RF input to the first intermediate node using a first feed-forward capacitor. 17. The method of claim 16, further comprising providing a second feed-forward path from the first intermediate node to the second intermediate node using a second feed-forward capacitor. 18. The method of claim 16, further comprising controlling a plurality of body voltages of the two or more pairs of anti-series MOS capacitors using a plurality of diodes to increase a power handling capability of the first variable capacitor cell. 19. The method of claim 16, wherein a third pair of the two or more pairs of anti-series MOS capacitors comprises a fifth MOS capacitor and a sixth MOS capacitor electrically connected in anti-series and electrically connected to one another at a third intermediate node, wherein the method further comprises providing a third feed-forward path from the second intermediate node to the third intermediate node using a third feed-forward capacitor. 20. An apparatus comprising: a radio frequency (RF) input;an RF output;a first variable capacitor cell of a plurality of variable capacitor cells electrically connected between the RF input and the RF output, the first capacitor cell having a capacitance configured to be controlled independently of another of the plurality of variable capacitor cells, wherein the first variable capacitor cell includes: two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series and electrically connected to one another at a first intermediate node, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series and electrically connected to one another at a second intermediate node; anda first feed-forward capacitor electrically connected between the RF input and the first intermediate node to provide a feed-forward path from the RF input to the first intermediate node.