Plasma-enhanced atomic layer deposition of conductive material over dielectric layers
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-023/52
H01L-029/40
H01L-023/00
C23C-016/32
C23C-016/36
C23C-016/455
H01L-021/28
H01L-029/49
H01L-029/51
출원번호
US-0021994
(2013-09-09)
등록번호
US-9466574
(2016-10-11)
발명자
/ 주소
Milligan, Robert B.
Li, Dong
Marcus, Steven
출원인 / 주소
ASM AMERICA, INC.
대리인 / 주소
Knobbe, Martens, Olson & Bear LLP
인용정보
피인용 횟수 :
0인용 특허 :
84
초록▼
Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process
Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process.
대표청구항▼
1. An integrated circuit device comprising: a metal oxide dielectric layer;an amorphous plasma barrier layer directly over and contacting the metal oxide dielectric layer, wherein the amorphous plasma barrier layer is between about 0.25 nm and about 1.75 nm thick and comprises an elemental metal, a
1. An integrated circuit device comprising: a metal oxide dielectric layer;an amorphous plasma barrier layer directly over and contacting the metal oxide dielectric layer, wherein the amorphous plasma barrier layer is between about 0.25 nm and about 1.75 nm thick and comprises an elemental metal, a conductive metal nitride, a metal carbide-nitride, a metal carbide, a metal silicon nitride, or a metal silicon carbide; anda consolidated crystalline conductive layer comprising a converted crystalline material layer directly over and contacting the amorphous plasma barrier layer and a conductive material layer directly over and contacting the converted crystalline material, wherein the conductive material is chosen from the group consisting of TaCN and TiN. 2. The integrated circuit device of claim 1, wherein the amorphous plasma barrier is between about 0.125 nm and about 0.875 nm thick. 3. The integrated circuit device of claim 2, wherein the amorphous plasma barrier is between about 0.05 nm and about 0.35 nm thick. 4. The integrated circuit device of claim 1, wherein the dielectric layer is chosen from the group consisting of Ta2O5, TiO2, HfO2, ZrO2, Al2O3, La2O3, HfSiOx, HfZrOx, HfAlOx, and LnAlOx. 5. The integrated circuit device of claim 4, wherein the dielectric layer is Al2O3. 6. The integrated circuit device of claim 1, wherein the amorphous plasma barrier comprises at least one of the group consisting of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Fe, Co, Ni, Pd, Pt, Rh, Ir, Ru and Os. 7. The integrated circuit device of claim 6, wherein the amorphous plasma barrier comprises TaCN. 8. The integrated circuit device of claim 1, wherein the conductive material layer comprises TaCN. 9. The integrated circuit device of claim 1, wherein the converted crystalline material and the conductive material align in their crystalline structure. 10. The integrated circuit device of claim 1, wherein the amorphous plasma barrier layer, the converted crystalline material and the conductive material each comprises the same metal. 11. The integrated circuit device of claim 10, wherein the amorphous plasma barrier layer, the converted crystalline material and the conductive material each comprises Ta. 12. The integrated circuit device of claim 1, wherein the amorphous plasma barrier layer, the converted crystalline material and the conductive material each comprises TaCN.
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