Method and system for controlling an interleaver
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03M-013/00
H03M-013/27
H04L-001/00
H04L-001/20
G06F-021/56
H03M-013/35
출원번호
US-0950127
(2015-11-24)
등록번호
US-9484958
(2016-11-01)
발명자
/ 주소
Starr, Thomas J. J.
출원인 / 주소
AT&T Intellectual Property I, L.P.
대리인 / 주소
Guntin & Gust, PLC
인용정보
피인용 횟수 :
0인용 특허 :
69
초록▼
Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control
Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.
대표청구항▼
1. A controller for an interleaver, comprising: a processing system including a processor; anda memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, comprising: receiving a first signal;receiving a second signal; andgenerating
1. A controller for an interleaver, comprising: a processing system including a processor; anda memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, comprising: receiving a first signal;receiving a second signal; andgenerating an interleaver control signal based on the first and second signals,wherein the first signal comprises a signal to noise ratio signal, andwherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal, andwherein the first and second signals are distinct signals. 2. The controller of claim 1, wherein the operations further comprise determining whether the first signal exceeds a threshold. 3. The controller of claim 1, wherein the operations further comprise determining whether the first signal exceeds a value. 4. The controller of claim 1, wherein the operations further comprise determining whether the second signal exceeds a threshold. 5. The controller of claim 1, wherein the operations further comprise determining whether the second signal exceeds a value. 6. The controller of claim 1, further comprising an interleaver coupled with the processing system, the interleaver being operative to receive the control signal. 7. The controller of claim 6, wherein the interleaver is operative to alter an interleaved signal in response to the interleaver control signal. 8. The controller of claim 6, wherein the interleaver is operative to alter an interleave depth of an interleaved signal in response to the interleaver control signal. 9. A method for controlling an interleaver, the method comprising: receiving, by a processing system comprising a processor, a first signal;receiving, by the processing system, a second signal; andgenerating, by the processing system, an interleaver control signal based on the first and second signals,wherein the first signal comprises a signal to noise ratio signal, andwherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal, andwherein the first and second signals are distinct signals. 10. The method of claim 9, further comprising determining whether the first signal exceeds a threshold. 11. The method of claim 9, further comprising determining whether the first signal exceeds a value. 12. The method of claim 9, further comprising determining whether the second signal exceeds a threshold. 13. The method of claim 9, further comprising determining whether the second signal exceeds a value. 14. The method of claim 9, further comprising transmitting the interleaver control signal to an interleaver. 15. A non-transitory, machine-readable storage medium, comprising executable instructions that, when executed by a processing system including a processor, facilitate performance of operations, comprising: receiving a first signal;receiving a second signal; andgenerating an interleaver control signal based on the first and second signals,wherein the first signal comprises a signal to noise ratio signal,wherein the second signal is selected from a group consisting of one of a data rate signal and a bit error rate signal, andwherein the first and second signals are distinct signals. 16. The non-transitory, machine-readable storage medium of claim 15, wherein the operations further comprise determining whether the data rate signal exceeds a threshold. 17. The non-transitory, machine-readable storage medium of claim 16, wherein the interleaver control signal instructs an interleaver to not perform interleaving when the data rate signal exceeds the threshold. 18. The non-transitory, machine-readable storage medium of claim 16, wherein the interleaver control signal ceases when the data rate signal exceeds the threshold. 19. The non-transitory, machine-readable storage medium of claim 15, wherein the interleaver control signal is proportional to the second signal. 20. The non-transitory, machine-readable storage medium of claim 15, wherein the interleaver control signal instructs an interleaver to perform interleaving proportional to the second signal.
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