3DIC system with a two stable state memory and back-bias region
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/115
G11C-016/02
H01L-029/78
G11C-011/404
G11C-011/4097
H01L-027/108
G11C-011/412
G11C-016/04
출원번호
US-0506160
(2014-10-03)
등록번호
US-9496271
(2016-11-15)
발명자
/ 주소
Or-Bach, Zvi
Widjaja, Yuniarto
출원인 / 주소
MONOLITHIC 3D INC.
대리인 / 주소
Tran & Associates
인용정보
피인용 횟수 :
2인용 특허 :
352
초록▼
A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at
A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.
대표청구항▼
1. A 3D IC based system, comprising: a first layer comprising first transistors;a second layer overlying said first layer, said second layer comprises a plurality of second transistors, wherein said second layer comprises at least one through second layer via having a diameter of less than 400 nm, a
1. A 3D IC based system, comprising: a first layer comprising first transistors;a second layer overlying said first layer, said second layer comprises a plurality of second transistors, wherein said second layer comprises at least one through second layer via having a diameter of less than 400 nm, andwherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region. 2. A 3D IC based system according to claim 1, wherein said back-bias region is disposed to one side of a channel region of said second transistors. 3. A 3D IC based system according to claim 1, wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region. 4. A 3D IC based system according to claim 1, wherein said back-bias region comprises polysilicon. 5. A 3D IC based system according to claim 1, wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region. 6. A 3D IC based system according to claim 1, wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure. 7. A 3D IC based system according to claim 1, wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors. 8. A 3D IC based system, comprising: a first layer comprising first transistors;a second layer overlying said first layer, said second layer comprises a plurality of second transistors, wherein said second layer thickness is less than 400 nm, andwherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region. 9. A 3D IC based system according to claim 8, wherein said back-bias region is disposed to one side of a channel region of said second transistors. 10. A 3D IC based system according to claim 8, wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region. 11. A 3D IC based system according to claim 8, wherein said back-bias region comprises polysilicon. 12. A 3D IC based system according to claim 8, wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region. 13. A 3D IC based system according to claim 8, wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure. 14. A 3D IC based system according to claim 8, wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors. 15. A 3D IC based system, comprising: a first layer comprising first transistors;a second layer overlying said first layer, said second layer comprises a plurality of second transistors, wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors, andwherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region. 16. A 3D IC based system according to claim 15, wherein said back-bias region is disposed to one side of said of a channel region of second transistors. 17. A 3D IC based system according to claim 15, wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region. 18. A 3D IC based system according to claim 15, wherein said back-bias region comprises polysilicon. 19. A 3D IC based system according to claim 15, wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region. 20. A 3D IC based system according to claim 15, wherein at least two of said plurality of second transistors are connected by a common doped mono crystal structure.
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