The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further inclu
The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
대표청구항▼
1. A semiconductor device comprising: a semiconductor substrate;a first array of electrodes disposed above the semiconductor substrate, wherein the first array of electrodes comprise a first metal-containing material, wherein the first metal is selected from a group consisting of: aluminum, nickel,
1. A semiconductor device comprising: a semiconductor substrate;a first array of electrodes disposed above the semiconductor substrate, wherein the first array of electrodes comprise a first metal-containing material, wherein the first metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten;a second array of electrodes disposed above the first array of electrodes, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein the second array of electrodes comprises a second metal-containing material; anda plurality of resistive switching nanostructures disposed between the first array of electrodes and the second array of electrodes, wherein each resistive switching nanostructure provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites; andwherein particles of the first metal derived from the first metal-containing material are diffused within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures, and wherein the particles of the first metal form a conductive filament within the one resistive switching nanostructure. 2. The semiconductor device of claim 1, wherein the undoped silicon-containing material is selected from a group consisting of: amorphous silicon and non-crystalline silicon. 3. The semiconductor device memory array of claim 1, wherein the second metal is selected from a group consisting of: nickel (Ni) and platinum (Pt). 4. The semiconductor device of claim 1, wherein the substrate comprises a plurality of circuits; andwherein the first array of electrodes and the second array of electrodes are coupled to at least one circuit of the plurality of circuits. 5. The semiconductor device of claim 4 wherein the circuit is selected from a group consisting of: a decoding circuit, a writing circuit, an erasing circuit and a reading circuit. 6. The semiconductor device of claim 4 wherein the circuit comprises a multi-level programming circuit. 7. The semiconductor device of claim 6 wherein the multi-level programming circuit comprises a plurality of resistances. 8. A method for fabricating a semiconductor device comprising: receiving a semiconductor substrate;forming a first array of electrodes above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material;forming a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites; andforming a second array of electrodes above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten;wherein particles of the second metal from the second metal-containing material are configured to diffuse within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures to thereby form a conductive filament within the one resistive switching nanostructure. 9. The method of claim 8 wherein the forming the plurality of resistive switching nanostructures comprises depositing a material selected from a group consisting of: amorphous silicon and non-crystalline silicon. 10. The method of claim 8 wherein the forming the first array comprises depositing a material selected from a group consisting of: nickel (Ni)-containing material and platinum (Pt) containing material. 11. The method of claim 8wherein receiving the semiconductor substrate comprises forming a plurality of circuits within the semiconductor substrate; andcoupling the first array of electrodes and the second array of electrodes to at least one circuit of the plurality of circuits. 12. The method of claim 11 wherein the forming the plurality of circuits comprises forming a circuit selected from a group consisting of” a decoding circuit, a writing circuit, an erasing circuit and a reading circuit. 13. The method of claim 11 wherein the forming the plurality of circuits comprises forming a multi-level programming circuit. 14. The method of claim 13 wherein the forming the multi-level programming circuit comprises forming a plurality of resistors. 15. A method for operating a semiconductor device comprising a semiconductor substrate comprises: applying a first voltage across a first electrode from a first array of electrodes and a first electrode from a second array of electrodes through a resistive switching nanostructure of a plurality of resistive switching nanostructures, to thereby induce a first current flow between the first electrode from the second array of electrodes and the first electrode from the first array of electrodes, wherein the first array of electrodes are disposed above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material, a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites, and wherein the second array of electrodes are disposed above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten; anddetermining a first resistance state of the resistive switching nanostructure in response to the first current flow. 16. The method of claim 15 further comprising: applying a second voltage across the first electrode from the second array of electrodes and the first electrode from the first array of electrodes, to thereby diffuse particles of the second metal from the first metal-containing material into defect sites of the resistive switching nanostructure, and to thereby form a conductive filament within the one resistive switching nanostructure; andterminating applying the second voltage, wherein the conductive filament remains formed within the one resistive switching nanostructure. 17. The method of claim 16 wherein after terminating applying the second voltage, the method further comprises: applying the first voltage across the first electrode from the second array of electrodes and the first electrode from the first array of electrodes through the resistive switching nanostructure to thereby induce a second current flow between the first electrode from the second array of electrodes and the first electrode from the first array of electrodes; anddetermining a second resistance state of the resistive switching nanostructure in response to the second current flow. 18. The method of claim 17 wherein the second current flow is larger than the first current flow. 19. The method of claim 16 wherein after terminating applying the second voltage, the method further comprises: applying the third voltage across the first electrode from the array of electrodes and the first electrode from the second array of electrodes through the resistive switching nanostructure to thereby withdraw at least some particles of the first metal from defect sites of the resistive switching nanostructure to the first electrode from the second array of electrodes, and to thereby reduce the conductive filament within the one resistive switching nanostructure. 20. The method of claim 19 wherein the second voltage has a polarity opposite of a polarity of the third voltage.
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