[특허]Power efficient multiplexer

Power efficient multiplexer 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-005/133 H03K-005/13 H03K-017/00 H03K-017/687 H03K-005/00
출원번호	US-0882264 (2015-10-13)
등록번호	US-9531361 (2016-12-27)
발명자 / 주소	Masleid, Robert Paul
출원인 / 주소	Intellectual Ventures Holding 81 LLC
인용정보	피인용 횟수 : 0 인용 특허 : 149

초록 ▼

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

대표청구항 ▼

1. A circuit, comprising: a transmission gate structure including a plurality of input nodes and an output node operable to output a signal; anda stacked inverter including: an inverter input node coupled to the output node;a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors;a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; andan inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. 2. The circuit of claim 1, wherein the first number of transistors is greater than the second number of transistors. 3. The circuit of claim 1, wherein the first number of transistors is less than the second number of transistors. 4. The circuit of claim 1, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node. 5. The circuit of claim 1, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node. 6. The circuit of claim 1, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes. 7. The circuit of claim 1, wherein the transmission gate structure further comprises: a first transmission gate coupled between a first input node of the plurality of input nodes and the output node; anda second transmission gate coupled between a second input node of the plurality of input nodes and the output node. 8. A circuit, comprising: a plurality of input nodes;an intermediate node;a plurality of transmission gates coupled to a respective one of the plurality of input nodes and coupled to the intermediate node that is operable to receive a signal from at least one of the transmission gates; anda stacked inverter including: an inverter input node coupled to the intermediate node;a low-to-high transition leg directly coupled to the intermediate node to receive the signal and comprising a first number of transistors;a high-to-low transition leg directly coupled to the intermediate node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; andan inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. 9. The circuit of claim 8, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes. 10. The circuit of claim 8, wherein the first number of transistors is greater than the second number of transistors. 11. The circuit of claim 8, wherein the first number of transistors is less than the second number of transistors. 12. The circuit of claim 8, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node. 13. The circuit of claim 8, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node. 14. A circuit, comprising: a latch;a transmission gate structure including a plurality of input nodes, an output node operable to output a signal, and a plurality of control nodes coupled to the latch; anda stacked inverter including: an inverter input node coupled to the output node;a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors;a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; andan inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. 15. The circuit of claim 14, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes. 16. The circuit of claim 14, wherein the first number of transistors is greater than the second number of transistors. 17. The circuit of claim 14, wherein the first number of transistors is less than the second number of transistors. 18. The circuit of claim 14, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node. 19. The circuit of claim 14, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node. 20. The circuit of claim 14, wherein the transmission gate structure further comprises: a first transmission gate coupled to a first plurality of the plurality of control nodes and coupled between a first input node of the plurality of input nodes and the output node; anda second transmission gate coupled to a second plurality of the plurality of control nodes and coupled between a second input node of the plurality of input nodes and the output node.

이 특허에 인용된 특허 (149)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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