Reestablishing synchronization in a memory system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-011/07
G06F-001/12
G06F-011/10
G06F-011/14
G06F-011/20
G06F-011/16
출원번호
US-0835258
(2013-03-15)
등록번호
US-9535778
(2017-01-03)
발명자
/ 주소
Gilda, Glenn D.
Meaney, Patrick J.
Papazova, Vesselina K.
Dodson, John S.
출원인 / 주소
INTERNATIONAL BUSINESS MACHINES CORPORATION
대리인 / 주소
Cantor Colburn LLP
인용정보
피인용 횟수 :
0인용 특허 :
16
초록▼
Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality
Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.
대표청구항▼
1. A system for reestablishing synchronization across multiple channels in a memory system within a computer, the system comprising: a plurality of channels within the computer each providing communication with a memory buffer chip and a plurality of memory devices; anda memory control unit coupled
1. A system for reestablishing synchronization across multiple channels in a memory system within a computer, the system comprising: a plurality of channels within the computer each providing communication with a memory buffer chip and a plurality of memory devices; anda memory control unit coupled to the plurality of channels within the computer, the memory control unit configured to perform a method comprising: receiving an out-of-synchronization indication associated with at least one of the channels;performing, by the memory control unit, a first stage of a three stage process of reestablishing synchronization comprising: selectively stopping new traffic on the plurality of channels;waiting for a first time period to expire;resuming traffic on the plurality of channels based on the first time period expiring;verifying that synchronization is reestablished for a second time period; andbased on determining that synchronization is not reestablished for the second time period, repeating the first stage of reestablishing synchronization for a number of times before performing a second stage of the three stage process of reestablishing synchronization;performing, by the memory control unit, the second stage of reestablishing synchronization comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;resuming traffic on the plurality of channels based on the first time period expiring; andverifying that synchronization is reestablished for the second time period; andperforming a third stage of the three stage process of reestablishing synchronization based on determining that a memory buffer chip out-of-sync condition exists, the third stage comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;waiting for a write reorder queue empty status indicator from the memory buffer chips before sending a synchronization command;sending the synchronization command to the memory buffer chips on each of the channels;waiting for a third time period to expire;verifying that a replay did not occur during the third time period, wherein the replay comprises a recovery retransmission sequence from a replay buffer that causes a faulty channel to go out of synchronization with non-faulty instances of the channels;waiting a fourth time period before resuming traffic on the plurality of channels;resuming traffic on the plurality of channels;verifying that synchronization is reestablished for the second time period; andbased on determining that synchronization is not reestablished for the second time period, repeating the third stage of reestablishing synchronization for a number of times before declaring a failure. 2. The system of claim 1, wherein performing the second stage of reestablishing synchronization further comprises: waiting for the write reorder queue empty status indicator from the memory buffer chips;decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress;based on determining that synchronization is not reestablished for the second time period, determining whether the memory buffer chip out-of-sync condition exists; andbased on determining that the memory buffer chip out-of-sync condition does not exist, repeating the second stage of reestablishing synchronization for a number of times before advancing to the third stage of reestablishing synchronization or declaring a failure. 3. The system of claim 1, wherein performing the first stage of reestablishing synchronization further comprises: decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress. 4. The system of claim 1, wherein selectively stopping new traffic on the plurality of channels further comprises: stopping the new traffic on the plurality of channels unless a skip counter is enabled and not exceeded. 5. A computer implemented method for reestablishing synchronization across multiple channels in a memory system within a computer, the method comprising: receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system within the computer, wherein the plurality of channels within the computer each provide communication with a memory buffer chip and a plurality of memory devices;performing, by a memory control unit in communication with the channels within the computer, a first stage of a three stage process of reestablishing synchronization comprising: selectively stopping new traffic on the plurality of channels;waiting for a first time period to expire;resuming traffic on the plurality of channels based on the first time period expiring;verifying that synchronization is reestablished for a second time period; and based on determining that synchronization is not reestablished for the second time period, repeating the first stage of reestablishing synchronization for a number of times before performing a second stage of the three stage process of reestablishing synchronization;performing, by the memory control unit, the second stage of reestablishing synchronization comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;resuming traffic on the plurality of channels based on the first time period expiring; andverifying that synchronization is reestablished for the second time period; andperforming a third stage of the three stage process of reestablishing synchronization based on determining that a memory buffer chip out-of-sync condition exists, the third stage comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;waiting for a write reorder queue empty status indicator from the memory buffer chips before sending a synchronization command;sending the synchronization command to the memory buffer chips on each of the channels;waiting for a third time period to expire;verifying that a replay did not occur during the third time period, wherein the replay comprises a recovery retransmission sequence from a replay buffer that causes a faulty channel to go out of synchronization with non-faulty instances of the channels;waiting a fourth time period before resuming traffic on the plurality of channels;resuming traffic on the plurality of channels;verifying that synchronization is reestablished for the second time period; andbased on determining that synchronization is not reestablished for the second time period, repeating the third stage of reestablishing synchronization for a number of times before declaring a failure. 6. The method of claim 5, wherein performing the second stage of reestablishing synchronization further comprises: waiting for the write reorder queue empty status indicator from the memory buffer chips;decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress;based on determining that synchronization is not reestablished for the second time period, determining whether the memory buffer chip out-of-sync condition exists; andbased on determining that the memory buffer chip out-of-sync condition does not exist, repeating the second stage of reestablishing synchronization for a number of times before advancing to the third stage of reestablishing synchronization or declaring a failure. 7. The method of claim 5, wherein performing the first stage of reestablishing synchronization further comprises: decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress. 8. A computer program product for reestablishing synchronization across multiple channels in a memory system within a computer, the computer program product comprising: a non-transitory machine readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system within the computer, wherein the plurality of channels within the computer each provide communication with a memory buffer chip and a plurality of memory devices:performing, by a memory control unit in communication with the channels within the computer, a first stage of a three stage process of reestablishing synchronization comprising: selectively stopping new traffic on the plurality of channels; waiting for a first time period to expire;resuming traffic on the plurality of channels based on the first time period expiring;verifying that synchronization is reestablished for a second time period; andbased on determining that synchronization is not reestablished for the second time period, repeating the first stage of reestablishing synchronization for a number of times before performing a second stage of the three stage process of reestablishing synchronization;performing, by the memory control unit, the second stage of reestablishing synchronization comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;resuming traffic on the plurality of channels based on the first time period expiring; andverifying that synchronization is reestablished for the second time period; andperforming a third stage of the three stage process of reestablishing synchronization based on determining that a memory buffer chip out-of-sync condition exists, the third stage comprising: stopping new traffic on the plurality of channels;waiting for outstanding traffic on the plurality of channels to complete;waiting for a write reorder queue empty status indicator from the memory buffer chips before sending a synchronization command;sending the synchronization command to the memory buffer chips on each of the channels;waiting for a third time period to expire;verifying that a replay did not occur during the third time period, wherein the replay comprises a recovery retransmission sequence from a replay buffer that causes a faulty channel to go out of synchronization with non-faulty instances of the channels;waiting a fourth time period before resuming traffic on the plurality of channels;resuming traffic on the plurality of channels;verifying that synchronization is reestablished for the second time period; andbased on determining that synchronization is not reestablished for the second time period, repeating the third stage of reestablishing synchronization for a number of times before declaring a failure. 9. The computer program product of claim 8, wherein performing the second stage of reestablishing synchronization further comprises: waiting for the write reorder queue empty status indicator from the memory buffer chips;decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress;based on determining that synchronization is not reestablished for the second time period, determining whether the memory buffer chip out-of-sync condition exists; andbased on determining that the memory buffer chip out-of-sync condition does not exist, repeating the second stage of reestablishing synchronization for a number of times before advancing to the third stage of reestablishing synchronization or declaring a failure. 10. The computer program product of claim 8, wherein performing the first stage of reestablishing synchronization further comprises: decrementing the first time period while waiting for the first time period to expire based on determining that the replay is not in progress.
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