최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0945361 (2015-11-18) |
등록번호 | US-9536899 (2017-01-03) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 2 인용 특허 : 558 |
A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate
A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.
1. A semiconductor chip, comprising: a region including a plurality of transistors, each of the plurality of transistors in the region forming part of a digital logic circuit associated with execution of one or more logic functions, the region including at least five conductive structures formed wit
1. A semiconductor chip, comprising: a region including a plurality of transistors, each of the plurality of transistors in the region forming part of a digital logic circuit associated with execution of one or more logic functions, the region including at least five conductive structures formed within the semiconductor chip, some of the at least five conductive structures forming at least one transistor gate electrode,each of the at least five conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least five conductive structures co-planar with each other,each of the at least five conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least five conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least five conductive structures is substantially straight,wherein the second edge of each of the at least five conductive structures is substantially straight,each of the at least five conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least five conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least five conductive structures,wherein the at least five conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,wherein the at least five conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any gate electrode formed by the second conductive structure is of the first transistor type,wherein the at least five conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any gate electrode formed by the third conductive structure is of the second transistor type,wherein the first conductive structure is positioned between the second and third conductive structures in a second direction perpendicular to the first direction,wherein a gate electrode of a third transistor of the first transistor type is formed by one of the at least five conductive structures,wherein a gate electrode of a third transistor of the second transistor type is formed by one of the at least five conductive structures,wherein a gate electrode of a fourth transistor of the first transistor type is formed by one of the at least five conductive structures,wherein a gate electrode of a fourth transistor of the second transistor type is formed by one of the at least five conductive structures,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least five conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least five conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,wherein the first and second transistors of the first transistor type are positioned adjacent to each other,wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type physically and electrically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node,wherein the first and second transistors of the second transistor type are positioned adjacent to each other,wherein the first transistor of the second transistor type includes a first diffusion terminal and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type physically and electrically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node,wherein the first transistor of the first transistor type includes a second diffusion terminal and the third transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type,wherein the second transistor of the first transistor type includes a second diffusion terminal and the fourth transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the fourth transistor of the first transistor type electrically connected to the second diffusion terminal of the second transistor of the first transistor type,wherein the first transistor of the second transistor type includes a second diffusion terminal and the third transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type,wherein the second transistor of the second transistor type includes a second diffusion terminal and the fourth transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the fourth transistor of the second transistor type electrically connected to the second diffusion terminal of the second transistor of the second transistor type,wherein the gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the fourth transistor of the second transistor type,wherein the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type,wherein the first conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the first conductive structure being the only portion of the first conductive structure above a substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the second conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the second conductive structure being the only portion of the second conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the third conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the third conductive structure being the only portion of the third conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein any conductive structures that make physical contact with one or both of the electrical connection area of the second conductive structure and the electrical connection area of the third conductive structure form part of an electrical connection between the second conductive structure and the third conductive structure;a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the at least five conductive structures, a portion of the first interconnect conductive structure positioned above the electrical connection area of the first conductive structure, the portion of the first interconnect conductive structure electrically connected to the first conductive structure;a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, a portion of the second interconnect conductive structure positioned above the electrical connection area of the second conductive structure, the portion of the second interconnect conductive structure electrically connected to the second conductive structure; anda third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, a portion of the third interconnect conductive structure positioned above the electrical connection area of the third conductive structure, the portion of the third interconnect conductive structure electrically connected to the third conductive structure. 2. The semiconductor chip as recited in claim 1, wherein the at least five conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms the gate electrode of the third transistor of the first transistor type, and wherein the fourth conductive structure also includes a portion that forms the gate electrode of the fourth transistor of the second transistor type, wherein the at least five conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms the gate electrode of the fourth transistor of the first transistor type, and wherein the fifth conductive structure also includes a portion that forms the gate electrode of the third transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the second conductive structure by a first pitch as measured in the second direction,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the third conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the second conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the third conductive structure is separated from the lengthwise centerline of the fourth conductive structure by the first pitch as measured in the second direction,wherein the second diffusion terminal of the second transistor of the first transistor type is physically connected to the first diffusion terminal of the fourth transistor of the first transistor type,wherein the second diffusion terminal of the second transistor of the second transistor type is physically connected to the first diffusion terminal of the fourth transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fourth conductive structure by a second pitch as measured in the second direction, the second pitch equal to two times the first pitch,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the second pitch as measured in the second direction,wherein the width as measured in the second direction of each of the first, second, third, fourth, and fifth conductive structures is less than 193 nanometers. 3. The semiconductor chip as recited in claim 2, wherein either A) the first diffusion terminal of the third transistor of the first transistor type is electrically connected to the second diffusion terminal of the first transistor of the first transistor type through at least one conductive structure formed in a level of the semiconductor chip above a diffusion level of the semiconductor chip, orB) the first diffusion terminal of the third transistor of the second transistor type is electrically connected to the second diffusion terminal of the first transistor of the second transistor type through at least one conductive structure formed in a level of the semiconductor chip above the diffusion level of the semiconductor chip, orboth A) and B). 4. The semiconductor chip as recited in claim 3, wherein the at least five conductive structures includes a sixth conductive structure that does not form a gate electrode of any transistor, and wherein the sixth conductive structure is positioned in a side-by-side manner with multiple adjacently positioned ones of the at least five conductive structures, such that a distance as measured in the second direction between the lengthwise centerline of the sixth conductive structure and lengthwise centerlines of each of the multiple adjacently positioned ones of the at least five conductive structures is equal to the first pitch, andwherein the width of the sixth conductive structure is substantially equal to the width of at least one of the multiple adjacently positioned ones of the at least five conductive structures, andwherein at least one of the multiple adjacently positioned ones of the at least five conductive structures forms at least one gate electrode of a transistor, andwherein either C) the first end of the sixth conductive structure is substantially positioned at a first line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the first transistor type is also substantially positioned at the first line extending in the second direction, orD) the second end of the sixth conductive structure is substantially positioned at a second line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the second transistor type is also substantially positioned at the second line extending in the second direction, orboth C) and D). 5. The semiconductor chip as recited in claim 4, wherein the common node includes a number of conductive structures that include at least one interconnect conductive structure within the first interconnect chip level of the semiconductor chip, wherein the electrical connection area of the first conductive structure extends over a first distance as measured in the first direction, a midpoint of the first distance corresponding to a first direction midpoint of the electrical connection area of the first conductive structure, the electrical connection area of the first conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the first conductive structure,wherein the electrical connection area of the second conductive structure extends over a second distance as measured in the first direction, a midpoint of the second distance corresponding to a first direction midpoint of the electrical connection area of the second conductive structure, the electrical connection area of the second conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the second conductive structure,wherein the electrical connection area of the third conductive structure extends over a third distance as measured in the first direction, a midpoint of the third distance corresponding to a first direction midpoint of the electrical connection area of the third conductive structure, the electrical connection area of the third conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the third conductive structure,wherein the second direction oriented centerline of the electrical connection area of the second conductive structure is substantially aligned with the second direction oriented centerline of the electrical connection area of the third conductive structure. 6. The semiconductor chip as recited in claim 5, wherein the length of the second conductive structure is substantially equal to the length of the first conductive structure. 7. The semiconductor chip as recited in claim 6, wherein the digital logic circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, wherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding upper surface, wherein an entirety of a periphery of the corresponding upper surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding upper surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end, wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges, wherein the corresponding first edge is substantially straight, and wherein the corresponding second edge is substantially straight, andwherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding lengthwise centerline extending along its upper surface from its first end to its second end and oriented substantially parallel to both its first edge and its second edge. 8. The semiconductor chip as recited in claim 7, further comprising: a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure; anda third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structure. 9. The semiconductor chip as recited in claim 4, wherein the fourth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fourth conductive structure being the only portion of the fourth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, wherein the fifth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fifth conductive structure being the only portion of the fifth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the length of the second conductive structure is substantially equal to the length of the first conductive structure,wherein the digital logic circuit is included within a single layout cell. 10. The semiconductor chip as recited in claim 9, further comprising: a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure; anda third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structure. 11. The semiconductor chip as recited in claim 4, wherein the width of the first conductive structure is less than 34 nanometers, wherein the width of the second conductive structure is less than 34 nanometers,wherein the width of the third conductive structure is less than 34 nanometers,wherein the width of the fourth conductive structure is less than 34 nanometers,wherein the width of the fifth conductive structure is less than 34 nanometers. 12. The semiconductor chip as recited in claim 1, wherein the at least five conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms the gate electrode of the third transistor of the first transistor type, and wherein the fourth conductive structure also includes a portion that forms the gate electrode of the fourth transistor of the second transistor type, wherein the fourth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fourth conductive structure being the only portion of the fourth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, wherein the at least five conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms the gate electrode of the fourth transistor of the first transistor type, and wherein the fifth conductive structure also includes a portion that forms the gate electrode of the third transistor of the second transistor type, wherein the fifth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fifth conductive structure being the only portion of the fifth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the lengthwise centerline of any of the first, second, third, fourth, and fifth conductive structures is separated from the lengthwise centerline of any other of the first, second, third, fourth, and fifth conductive structures by an integer multiple of a fixed pitch as measured in the second direction,wherein the width of the first conductive structure is less than 193 nanometers,wherein the width of the second conductive structure is less than 193 nanometers,wherein the width of the third conductive structure is less than 193 nanometers,wherein the width of the fourth conductive structure is less than 193 nanometers,wherein the width of the fifth conductive structure is less than 193 nanometers,the semiconductor chip including a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;the semiconductor chip including a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure;the semiconductor chip including a third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structurethe semiconductor chip including a fourth gate contact in physical connection with the electrical connection area of the fourth conductive structure, the fourth gate contact configured to extend from the electrical connection area of the fourth conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the fourth conductive structure, andthe semiconductor chip including a fifth gate contact in physical connection with the electrical connection area of the fifth conductive structure, the fifth gate contact configured to extend from the electrical connection area of the fifth conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the fifth conductive structure. 13. The semiconductor chip as recited in claim 12, wherein the at least five conductive structures includes a sixth conductive structure that does not form a gate electrode of any transistor, and wherein the sixth conductive structure is positioned in a side-by-side manner with multiple adjacently positioned ones of the at least five conductive structures, such that a distance as measured in the second direction between the lengthwise centerline of the sixth conductive structure and lengthwise centerlines of each of the multiple adjacently positioned ones of the at least five conductive structures is equal to the first pitch, andwherein the width of the sixth conductive structure is substantially equal to the width of at least one of the multiple adjacently positioned ones of the at least five conductive structures, andwherein at least one of the multiple adjacently positioned ones of the at least five conductive structures forms at least one gate electrode of a transistor, andwherein either A) the first end of the sixth conductive structure is substantially positioned at a first line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the first transistor type is also substantially positioned at the first line extending in the second direction, orB) the second end of the sixth conductive structure is substantially positioned at a second line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the second transistor type is also substantially positioned at the second line extending in the second direction, orboth A) and B). 14. The semiconductor chip as recited in claim 13, wherein the digital logic circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, wherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding upper surface, wherein an entirety of a periphery of the corresponding upper surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding upper surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end, wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges, wherein the corresponding first edge is substantially straight, wherein the corresponding second edge is substantially straight, andwherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding lengthwise centerline extending along its upper surface from its first end to its second end and oriented substantially parallel to both its first edge and its second edge. 15. The semiconductor chip as recited in claim 1, wherein the at least five conductive structures includes at least one conductive structure of a first extension type defined to form at least one gate electrode of at least one transistor of the first transistor type, wherein any transistor having its gate electrode formed by the at least one conductive structure of the first extension type is of the first transistor type, wherein the at least one conductive structure of the first extension type extends lengthwise in the first direction through the inner sub-region of the region and completely past a diffusion terminal of at least one transistor of the second transistor type, and wherein the at least five conductive structures includes at least one conductive structure of a second extension type defined to form at least one gate electrode of at least one transistor of the second transistor type, wherein any transistor having its gate electrode formed by the at least one conductive structure of the second extension type is of the second transistor type, wherein the at least one conductive structure of the second extension type extends lengthwise in the first direction through the inner sub-region of the region and completely past a diffusion terminal of at least one transistor of the first transistor type. 16. The semiconductor chip as recited in claim 15, wherein the at least one conductive structure of the first extension type is the second conductive structure or the at least one conductive structure of the second extension type is the third linear-shaped conductive structure. 17. The semiconductor chip as recited in claim 16, wherein the at least one conductive structure of the first extension type extends lengthwise in the first direction between at least two diffusion terminals of the second diffusion type, or wherein the at least one conductive structure of the second extension type extends lengthwise in the first direction between at least two diffusion terminals of the first diffusion type, orwherein the at least one conductive structure of the first extension type extends lengthwise in the first direction between at least two diffusion terminals of the second diffusion type and the at least one conductive structure of the second extension type extends lengthwise in the first direction between at least two diffusion terminals of the first diffusion type. 18. The semiconductor chip as recited in claim 17, wherein the at least one conductive structure of the first extension type is the second conductive structure, the second conductive structure extending lengthwise in the first direction between at least two diffusion terminals of the second diffusion type, and wherein the at least one conductive structure of the second extension type is the third linear-shaped conductive structure, the third conductive structure extending lengthwise in the first direction between at least two diffusion terminals of the first diffusion type. 19. The semiconductor chip as recited in claim 18, wherein the at least five conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms the gate electrode of the third transistor of the first transistor type, and wherein the fourth conductive structure also includes a portion that forms the gate electrode of the fourth transistor of the second transistor type, wherein the at least five conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms the gate electrode of the fourth transistor of the first transistor type, and wherein the fifth conductive structure also includes a portion that forms the gate electrode of the third transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the second conductive structure by a first pitch as measured in the second direction,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the third conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the second conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the third conductive structure is separated from the lengthwise centerline of the fourth conductive structure by the first pitch as measured in the second direction,wherein the second diffusion terminal of the second transistor of the first transistor type is physically connected to the first diffusion terminal of the fourth transistor of the first transistor type,wherein the second diffusion terminal of the second transistor of the second transistor type is physically connected to the first diffusion terminal of the fourth transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fourth conductive structure by a second pitch as measured in the second direction, the second pitch equal to two times the first pitch,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the second pitch as measured in the second direction,wherein the width as measured in the second direction of each of the first, second, third, fourth, and fifth conductive structures is less than 193 nanometers. 20. The semiconductor chip as recited in claim 19, wherein the digital logic circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, wherein each of the multiple interconnect conductive structures that form part of any electrical connection within the integrated circuit is configured to have a corresponding upper surface, wherein an entirety of a periphery of the corresponding upper surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding upper surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end, wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges, wherein the corresponding first edge is substantially straight, wherein the corresponding second edge is substantially straight, andwherein each of the multiple interconnect conductive structures that form part of any electrical connection within the integrated circuit is configured to have a corresponding lengthwise centerline extending along its upper surface from its first end to its second end and oriented substantially parallel to both its first edge and its second edge. 21. The semiconductor chip as recited in claim 19, further comprising: a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure; anda third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structure. 22. The semiconductor chip as recited in claim 16, wherein the at least five conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms the gate electrode of the third transistor of the first transistor type, and wherein the fourth conductive structure also includes a portion that forms the gate electrode of the fourth transistor of the second transistor type, wherein the at least five conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms the gate electrode of the fourth transistor of the first transistor type, and wherein the fifth conductive structure also includes a portion that forms the gate electrode of the third transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the second conductive structure by a first pitch as measured in the second direction,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the third conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the second conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the third conductive structure is separated from the lengthwise centerline of the fourth conductive structure by the first pitch as measured in the second direction,wherein the second diffusion terminal of the second transistor of the first transistor type is physically connected to the first diffusion terminal of the fourth transistor of the first transistor type,wherein the second diffusion terminal of the second transistor of the second transistor type is physically connected to the first diffusion terminal of the fourth transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fourth conductive structure by a second pitch as measured in the second direction, the second pitch equal to two times the first pitch,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the second pitch as measured in the second direction,wherein the width as measured in the second direction of each of the first, second, third, fourth, and fifth conductive structures is less than 193 nanometers. 23. The semiconductor chip as recited in claim 22, wherein the common node includes a number of conductive structures that include at least one interconnect conductive structure within the first interconnect chip level of the semiconductor chip. 24. The semiconductor chip as recited in claim 23, wherein the electrical connection area of the first conductive structure extends over a first distance as measured in the first direction, a midpoint of the first distance corresponding to a first direction midpoint of the electrical connection area of the first conductive structure, the electrical connection area of the first conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the first conductive structure, wherein the electrical connection area of the second conductive structure extends over a second distance as measured in the first direction, a midpoint of the second distance corresponding to a first direction midpoint of the electrical connection area of the second conductive structure, the electrical connection area of the second conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the second conductive structure,wherein the electrical connection area of the third conductive structure extends over a third distance as measured in the first direction, a midpoint of the third distance corresponding to a first direction midpoint of the electrical connection area of the third conductive structure, the electrical connection area of the third conductive structure having a second direction oriented centerline extending in the second direction through the first direction midpoint of the electrical connection area of the third conductive structure,wherein the second direction oriented centerline of the electrical connection area of the second conductive structure is substantially aligned with the second direction oriented centerline of the electrical connection area of the third conductive structure. 25. The semiconductor chip as recited in claim 24, further comprising: a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure; anda third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structure. 26. The semiconductor chip as recited in claim 24, wherein the digital logic circuit includes electrical connections formed by one or more of multiple interconnect conductive structures within one or more of a number of interconnect chip levels, the number of interconnect chip levels including the first interconnect chip level and any interconnect chip level above the first interconnect chip level, wherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding upper surface, wherein an entirety of a periphery of the corresponding upper surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding upper surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end, wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges, wherein the corresponding first edge is substantially straight, wherein the corresponding second edge is substantially straight, andwherein each of the multiple interconnect conductive structures that form part of any electrical connection within the digital logic circuit is configured to have a corresponding lengthwise centerline extending along its upper surface from its first end to its second end and oriented substantially parallel to both its first edge and its second edge. 27. The semiconductor chip as recited in claim 26, further comprising: a first gate contact in physical connection with the electrical connection area of the first conductive structure, the first gate contact configured to extend from the electrical connection area of the first conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the first conductive structure;a second gate contact in physical connection with the electrical connection area of the second conductive structure, the second gate contact configured to extend from the electrical connection area of the second conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the second conductive structure; anda third gate contact in physical connection with the electrical connection area of the third conductive structure, the third gate contact configured to extend from the electrical connection area of the third conductive structure through a dielectric material to physically contact a portion of another conductive structure located above the electrical connection area of the third conductive structure. 28. The semiconductor chip as recited in claim 27, wherein the digital logic circuit is included within a single layout cell. 29. A method for manufacturing a semiconductor chip, comprising: forming a plurality of transistors within a region of the semiconductor chip, each of the plurality of transistors in the region forming part of a digital logic circuit associated with execution of one or more logic functions, the plurality of transistors having respective gate electrodes formed by some of at least five conductive structures present within the region,wherein forming the plurality of transistors includes forming each of the at least five conductive structures to respectively have a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least five conductive structures co-planar with each other,each of the at least five conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least five conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least five conductive structures is substantially straight,wherein the second edge of each of the at least five conductive structures is substantially straight,each of the at least five conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least five conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least five conductive structures,wherein the at least five conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,wherein the at least five conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any gate electrode formed by the second conductive structure is of the first transistor type,wherein the at least five conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any gate electrode formed by the third conductive structure is of the second transistor type,wherein the at least five conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, and wherein the fourth conductive structure also includes a portion that forms a gate electrode of a fourth transistor of the second transistor type,wherein the at least five conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a fourth transistor of the first transistor type, and wherein the fifth conductive structure also includes a portion that forms a gate electrode of a third transistor of the second transistor type,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the second conductive structure by a first pitch as measured in the second direction,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the third conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the second conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the third conductive structure is separated from the lengthwise centerline of the fourth conductive structure by the first pitch as measured in the second direction,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fourth conductive structure by a second pitch as measured in the second direction, the second pitch equal to two times the first pitch,wherein the lengthwise centerline of the first conductive structure is separated from the lengthwise centerline of the fifth conductive structure by the second pitch as measured in the second direction,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least five conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least five conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,wherein forming the plurality of transistors includes positioning the first conductive structure between the second and third conductive structures in a second direction perpendicular to the first direction,wherein forming the plurality of transistors includes positioning the first and second transistors of the first transistor type adjacent to each other,wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type physically and electrically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node,wherein forming the plurality of transistors includes positioning the first and second transistors of the second transistor type adjacent to each other,wherein the first transistor of the second transistor type includes a first diffusion terminal and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type physically and electrically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node,wherein the first transistor of the first transistor type includes a second diffusion terminal and the third transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type,wherein the second transistor of the first transistor type includes a second diffusion terminal and the fourth transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the fourth transistor of the first transistor type physically and electrically connected to the second diffusion terminal of the second transistor of the first transistor type,wherein the first transistor of the second transistor type includes a second diffusion terminal and the third transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type,wherein the second transistor of the second transistor type includes a second diffusion terminal and the fourth transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the fourth transistor of the second transistor type physically and electrically connected to the second diffusion terminal of the second transistor of the second transistor type,wherein the gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the fourth transistor of the second transistor type,wherein the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type,wherein the first conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the first conductive structure being the only portion of the first conductive structure above a substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the second conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the second conductive structure being the only portion of the second conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the third conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the third conductive structure being the only portion of the third conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein any conductive structures that make physical contact with one or both of the electrical connection area of the second conductive structure and the electrical connection area of the third conductive structure form part of an electrical connection between the second conductive structure and the third conductive structure,wherein the fourth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fourth conductive structure being the only portion of the fourth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the fifth conductive structure includes an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fifth conductive structure being the only portion of the fifth conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit,wherein the width as measured in the second direction of each of the first, second, third, fourth, and fifth conductive structures is less than 193 nanometers,wherein the at least five conductive structures includes a sixth conductive structure that does not form a gate electrode of any transistor,wherein the sixth conductive structure is positioned in a side-by-side manner with multiple adjacently positioned ones of the at least five conductive structures, such that a distance as measured in the second direction between the lengthwise centerline of the sixth conductive structure and lengthwise centerlines of each of the multiple adjacently positioned ones of the at least five conductive structures is equal to the first pitch,wherein the width of the sixth conductive structure is substantially equal to the width of at least one of the multiple adjacently positioned ones of the at least five conductive structures,wherein at least one of the multiple adjacently positioned ones of the at least five conductive structures forms at least one gate electrode of a transistor, andwherein either A) the first end of the sixth conductive structure is substantially positioned at a first line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the first transistor type is also substantially positioned at the first line extending in the second direction, orB) the second end of the sixth conductive structure is substantially positioned at a second line extending in the second direction and an end of another of the at least five conductive structures that forms a gate electrode of a transistor of the second transistor type is also substantially positioned at the second line extending in the second direction, orboth A) and B);forming a first interconnect conductive structure within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the at least five conductive structures, a portion of the first interconnect conductive structure positioned above the electrical connection area of the first conductive structure, the portion of the first interconnect conductive structure electrically connected to the first conductive structure;forming a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, a portion of the second interconnect conductive structure positioned above the electrical connection area of the second conductive structure, the portion of the second interconnect conductive structure electrically connected to the second conductive structure; andforming a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, a portion of the third interconnect conductive structure positioned above the electrical connection area of the third conductive structure, the portion of the third interconnect conductive structure electrically connected to the third conductive structure,wherein the digital logic circuit is included within a single layout cell. 30. The method as recited in claim 29, wherein the width as measured in the second direction of each of the first, second, third, fourth, fifth, and sixth conductive structures is less than 34 nanometers.
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