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Deposition of titanium nanolaminates for use in integrated circuit fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-016/44
  • C23C-016/455
  • H01L-021/02
  • H01L-021/311
  • H01L-021/28
  • H01L-049/02
  • C23C-016/40
출원번호 US-0835456 (2015-08-25)
등록번호 US-9540729 (2017-01-10)
발명자 / 주소
  • Okura, Seiji
  • Suemori, Hidemi
  • Pore, Viljami J.
출원인 / 주소
  • ASM IP HOLDING B.V.
대리인 / 주소
    Knobbe Martens Olson & Bear LLP
인용정보 피인용 횟수 : 1  인용 특허 : 38

초록

Processes are provided for depositing titanium nanolaminate thin films that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. In some embodiments a titanium nanolaminate film comprising titanium oxide layers and titanium nitrid

대표청구항

1. A process for depositing a titanium nanolaminate thin film in integrated circuit fabrication comprising: depositing a first titanium material layer comprising nitrogen, oxygen, and/or carbon by at least one cycle of a first deposition process;depositing a second titanium oxide layer by at least o

이 특허에 인용된 특허 (38)

  1. Vaartstra, Brian A., Aluminum-containing material and atomic layer deposition methods.
  2. Visokay, Mark Robert; Rotondaro, Antonio Luis Pacheco; Colombo, Luigi, Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing.
  3. Yeong-kwan Kim KR; In-seon Park KR; Sang-min Lee KR; Chang-soo Park KR, Capacitor for a semiconductor device and method for forming the same.
  4. Bai Gang ; Liang Chunlin, Complementary metal gates and a process for implementation.
  5. Bhattacharyya, Arup, Decoupling capacitor for high frequency noise immunity.
  6. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  7. Mantese, Joseph V.; Eddy, David S.; Aukland, Neil R.; Thompson, Margarita P.; Wang, Su Chee S., Fuel cell with metal alloy contacts that form passivating conductive oxide surfaces.
  8. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Graded thin films.
  9. Buchanan, Douglas A.; Callegari, Alessandro C.; Gribelyuk, Michael A.; Jamison, Paul C.; Neumayer, Deborah Ann, High mobility FETS using A1203 as a gate oxide.
  10. Fu, Tzy-Tzan; Lin, Kuan-Ting; Chou, Chao-Sheng, Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4.
  11. Haukka, Suvi; Shero, Eric; Pomarede, Christophe; Hub Maes, Jan Willem; Tuominen, Marko, Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer.
  12. Chau Robert S. (Beaverton OR) Fraser David B. (Danville CA) Cadien Kenneth C. (Portland OR) Raghavan Gopal (Mountain View CA) Yau Leopoldo D. (Portland OR), MOS transistor having a composite gate electrode and method of fabrication.
  13. Yu Bin, MOS transistor with dual metal gate structure.
  14. Park, Dae-Gyu; Jang, Se-Aug; Lee, Jeong-Youb; Cho, Hung-Jae; Kim, Jung-Ho, Method for forming aluminum oxide as a gate dielectric.
  15. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
  16. Sergey D. Lopatin ; Carl Galewski ; Takeshi T. N. Nogami JP, Method of copper interconnect formation using atomic layer copper deposition.
  17. Haukka, Suvi; Huotari, Hannu, Method of depositing barrier layer for metal gates.
  18. Schinella, Richard, Method of forming SiGe gate electrode.
  19. Ma, Yanjun; Ono, Yoshi, Method of forming a multilayer dielectric stack.
  20. Huotari,Hannu; Haukka,Suvi; Tuominen,Marko, Method of forming an electrode with adjusted work function.
  21. Wilk Glen D. ; Summerfelt Scott R., Method of forming dual metal gate structures or CMOS devices.
  22. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Method of forming graded thin films using alternating pulses of vapor phase reactants.
  23. Chau Robert S. ; Fraser David B. ; Cadien Kenneth C. ; Raghavan Gopal ; Yau Leopoldo D., Method of frabricating a MOS transistor having a composite gate electrode.
  24. Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
  25. Cha, Tae Ho; Jang, Se Aug; Kim, Tae Kyun; Park, Dea Gyu; Yeo, In Seok; Park, Jin Won, Method of manufacturing a transistor in a semiconductor device.
  26. Park, Dae Gyu; Cha, Tae Ho; Jang, Se Aug; Cho, Heung Jae; Kim, Tae Kyun; Lim, Kwan Yong; Yeo, In Seok; Park, Jin Won, Method of manufacturing semiconductor devices with titanium aluminum nitride work function.
  27. Pore, Viljami; Ritala, Mikko; Leskelä, Markku, Methods for forming conductive titanium oxide thin films.
  28. Haukka, Suvi P.; Tuominen, Marko, Methods for making a dielectric stack in an integrated circuit.
  29. Wenhe Lin SG; Mei-Sheng Zhou SG; Kin Leong Pey SG; Simon Chooi SG, Methods to form dual metal gates by incorporating metals and their conductive oxides.
  30. Yanjun Ma ; Yoshi Ono, Multilayer dielectric stack and method.
  31. Senzaki, Yoshihide, Multilayer high κ dielectric films.
  32. Ngai, Tat; Nguyen, Bich-Yen; Kaushik, Vidya S.; Schaeffer, Jamie K., Semiconductor device and a method therefor.
  33. Chabal, Yves Jean; Green, Martin Laurence; Wilk, Glen David, Semiconductor device having a high-K gate dielectric and method of manufacture thereof.
  34. Isik C. Kizilyalli ; Ranbir Singh ; Lori Stirling, Semiconductor device having a metal gate with a work function compatible with a semiconductor device.
  35. Gardner Mark I. ; Fulford H. Jim ; May Charles E. ; Hause Fred ; Kwong Dim-Lee, Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof.
  36. Pomarede, Christophe F.; Roberts, Jeff; Shero, Eric J., Surface preparation prior to deposition.
  37. Hegde, Rama I.; Mogab, Joe; Tobin, Philip J.; Tseng, Hsing H.; Liu, Chun-Li; Borucki, Leonard J.; Merchant, Tushar P.; Hobbs, Christopher C.; Gilmer, David C., Transistor with layered high-K gate dielectric and method therefor.
  38. Jun-Fei Zheng ; Brian Doyle ; Gang Bai ; Chunlin Liang, Work function tuning for MOSFET gate electrodes.

이 특허를 인용한 특허 (1)

  1. Pore, Viljami J.; Okura, Seiji; Suemori, Hidemi, Process for deposition of titanium oxynitride for use in integrated circuit fabrication.
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