Low power bandgap circuit device with zero temperature coefficient current generation
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/10
G05F-003/16
출원번호
US-0625227
(2015-02-18)
등록번호
US-9547325
(2017-01-17)
발명자
/ 주소
Vecera, Dusan
출원인 / 주소
INVENSENSE, INC.
대리인 / 주소
Amin, Turocy & Watson, LLP
인용정보
피인용 횟수 :
0인용 특허 :
19
초록▼
A low power bandgap circuit device that generates temperature independent reference voltages and/or zero temperature coefficient currents is disclosed. The circuit comprises a first pair of transistors, an amplifier, a star connected resistive network, and a second pair of transistors, wherein zero
A low power bandgap circuit device that generates temperature independent reference voltages and/or zero temperature coefficient currents is disclosed. The circuit comprises a first pair of transistors, an amplifier, a star connected resistive network, and a second pair of transistors, wherein zero temperature coefficient currents are generated through mirroring and reuse of current from the star connected resistive network.
대표청구항▼
1. A low power bandgap reference circuit, comprising: a first resistive element coupled to a second resistive element and a third resistive element, the first resistive element, the second resistive element, and the third resistive element configured to form a star resistor network, wherein a first
1. A low power bandgap reference circuit, comprising: a first resistive element coupled to a second resistive element and a third resistive element, the first resistive element, the second resistive element, and the third resistive element configured to form a star resistor network, wherein a first resistance associated with the first resistive element is determined as a function of a first reference resistive element, a second resistance associated with the second resistive element is determined as a function of a second reference resistive element, and a third resistance associated with the third resistive element is determined as a function of the first reference resistive element and the second reference resistive element. 2. The low power bandgap reference circuit of claim 1, wherein the star resistor network is connected between a summing input of an amplifier and a ground node. 3. The low power bandgap reference circuit of claim 1, wherein a temperature independent voltage is generated by a flow of current through a first bipolar transistor and a second bipolar transistor. 4. The low power bandgap reference circuit of claim 1, wherein a value of the first resistive element is determined as a fraction of a resistive value of the first reference resistive element denominated by a value of a defined design parameter, wherein the value of the defined design parameter has a value greater than one. 5. The low power bandgap reference circuit of claim 4, wherein a value of the second resistive element is determined as a fraction of a resistive value of the second reference resistive element denominated by the value of the defined design parameter. 6. The low power bandgap reference circuit of claim 4, wherein a value of the third resistive element is determined as a fraction of a product of the resistive value of the first reference resistive element and the resistive value of the second reference resistive element denominated by a sum of the value of the first reference resistive element and the value of the second reference resistive element multiplied by a value of one less than the value of the defined design parameter denominated by the value of the defined design parameter. 7. The low power bandgap reference circuit of claim 1, wherein the third resistive element comprises a first sub resistive element and a second sub resistive element, wherein the first sub resistive element and the second sub resistive element are coupled in series. 8. The low power bandgap reference circuit of claim 7, wherein the star resistor network is coupled to a fourth element. 9. The low power bandgap reference circuit of claim 8, wherein the fourth resistive element is a first n-channel metal oxide semiconductor device. 10. The low power bandgap reference circuit of claim 9, wherein a gate of the first n-channel metal oxide semiconductor device is coupled to a source of the first n-channel metal oxide semiconductor device. 11. The low power bandgap reference circuit of claim 9, wherein a gate of the first n-channel oxide semiconductor device is coupled to a defined location between the first sub resistive element and the second sub resistive element of the third resistive element. 12. The low power bandgap reference circuit of claim 10, wherein a gate of the first n-channel metal oxide semiconductor device is coupled to a gate of a second n-channel metal oxide semiconductor device. 13. The low power bandgap reference circuit of claim 11, wherein a gate of the first n-channel metal oxide semiconductor device is coupled to a gate of a second n-channel oxide semiconductor device. 14. The low power bandgap reference circuit of claim 13, wherein a drain of the second n-channel metal oxide semiconductor device is coupled to a current summation circuit, wherein a zero temperature coefficient current is generated. 15. The low power bandgap reference circuit of claim 14, wherein a drain of a p-channel metal oxide semiconductor device is coupled to the current summation circuit. 16. The low power bandgap reference circuit of claim 15, wherein the drain of the p-channel metal oxide semiconductor device supplied positive temperature coefficient current to the current summation circuit. 17. The low power bandgap reference circuit of claim 12, wherein a drain of the second n-channel metal oxide semiconductor device supplies current with a negative temperature coefficient. 18. The low power bandgap reference circuit of claim 8, wherein a flow of negative temperature coefficient current flows through the fourth element. 19. A low power bandgap circuit device for providing a temperature independent reference voltage and a zero temperature coefficient current, comprising: a first bipolar transistor device coupled to a second bipolar transistor device;a loop amplifier device coupled to the first bipolar transistor device;a star connected resistor network coupled in parallel to the first bipolar transistor device and the second bipolar transistor device, wherein the star connected resistor network comprises a first resistive element coupled to a second resistive element, the first resistive element coupled to a third resistive element, and the second resistive element coupled to the third resistive element, and wherein a first resistance value associated with the first resistive element is determined based on a first reference resistive element, a second resistance value associated with the second resistive element is determined based on a second reference resistive element, and a third resistance value associated with the third resistive element is determined based on first reference resistive element and the second reference resistive element; anda first p-channel metal oxide semiconductor transistor device and a second p-channel metal oxide semiconductor transistor device coupled in series, wherein an emitter of the first bipolar transistor device is coupled to the first p-channel metal oxide semiconductor transistor device and an emitter of the second bipolar transistor device is coupled to an emitter of the second bipolar transistor device through a resistor. 20. The low power bandgap circuit device of claim 19, further comprising a third p-channel metal oxide semiconductor transistor device coupled in series to the second p-channel metal oxide semiconductor transistor device, wherein the drain of the third p-channel metal oxide semiconductor transistor device generates the temperature independent reference voltage. 21. The low power bandgap circuit device of claim 20, further comprising a fourth p-channel metal oxide semiconductor transistor device coupled in series to the third p-channel metal oxide semiconductor transistor device, wherein a drain of the forth p-channel metal oxide semiconductor transistor device supplies positive temperature coefficient current to a summation circuit device. 22. The low power bandgap circuit device of claim 19, wherein the resistance value associated with the first resistive element is determined as a function of a fractional value of a resistance value associated with the first reference resistive element divided by a value of a design parameter, wherein the value of the design parameter is value greater than one. 23. The low power bandgap circuit device of claim 19, wherein the second resistance value associated with the second resistive element is determined as function of a fractional value of a resistance value associated with the second reference resistive element divided by the value of the design parameter. 24. The low power bandgap circuit device of claim 22, wherein the third resistance value associated with the third resistive element is determined as a function of a fractional value of a product of the first reference resistive element and the second reference resistive element divided by a value of a sum of the first reference resistive element and the second reference resistive element multiplied by a value one less than the value of the design parameter divided by the value of the design parameter. 25. The low power bandgap circuit device of claim 19, wherein the star resistor network is connected to a summing input of the amplifier device. 26. The low power bandgap circuit device of claim 19, wherein the star resistor network is coupled to a first n-channel metal oxide semiconductor device. 27. The low power bandgap circuit device of claim 25, wherein the first n-channel metal oxide semiconductor device is coupled to a second n-channel metal oxide semiconductor device. 28. The low power bandgap circuit device of claim 26, wherein a drain of the second n-channel metal oxide semiconductor device is coupled to a summation circuit device and a drain of the second n-channel metal oxide semiconductor device outputs a negative temperature coefficient current. 29. The low power bandgap circuit device of claim 28, wherein the summation circuit device combines a positive temperature coefficient current supplied from a drain of a fourth transistor device with the negative temperature coefficient current to generate the zero temperature coefficient current.
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이 특허에 인용된 특허 (19)
Neaves,Philip, Bandgap reference circuit with a shared resistive network.
Zanchi, Alfio; Thomas, David M.; Sousa, Joseph L.; Thomas, Andrew J.; Steensgaard-Madsen, Jesper, Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias.
Lakshmikumar Kadaba R. (Wescosville PA) Nagaraj Krishnaswamy (Somerville NJ) Rich David Arthur (Woodmere NY) Tham Khong-Meng (Reading PA), PTAT current source.
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