A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.
대표청구항▼
1. A multiprocessor system comprising: a plurality of data processing units, each of the data processing units:(a) being programmable; and(b) being adaptable for sequentially processing data in a clocked manner; and including (c1) at least one Arithmetic Logic Unit (ALU), and(c2) at least one data r
1. A multiprocessor system comprising: a plurality of data processing units, each of the data processing units:(a) being programmable; and(b) being adaptable for sequentially processing data in a clocked manner; and including (c1) at least one Arithmetic Logic Unit (ALU), and(c2) at least one data register set for storing intermediate results in sequential data processing;at least one bus system for at least interconnecting at least some of the data processing units, each being provided a supply voltage by a voltage supply;wherein for at least some of the data processing units, the clock frequency is adjustable at runtime without affecting the clock frequency of at least one of: one other of the data processing units, andthe bus system; andwherein the voltage supply is adapted to supply higher supply voltages for data processing at higher clock frequencies. 2. The system of claim 1 wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to a state of the multiprocessor system. 3. The system of claim 1 wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to a state of the data processing entity. 4. The system of claim 1 wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to a state of others of the data processing units. 5. The system of claim 1 wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to a priority of a sequential task. 6. The system of claim 1, wherein the processor is adapted to reduce the supply voltage when the clock frequency is reduced. 7. The system of claim 6 adapted to subsequently reduce the clock frequency in accordance with a hysteresis characteristics. 8. The system of claim 1 further comprising: a heterogeneous plurality of clocked data processing units. 9. The system of claim 8 adapted to subsequently reduce the clock frequency in accordance with a hysteresis characteristics. 10. The system of claim 1, further comprising: a plurality of temperature sensors and a heterogeneous plurality of clocked data processing units; and whereinthe multiprocessor having a plurality of regions, a temperature sensor being provided for each of said plurality of regions to measure the temperature of said specific region; andthe clock frequencies of said data processing units being dynamically adjustable in accordance with the sensed temperatures. 11. The system of claim 10 adapted to subsequently reduce the clock frequency in accordance with a hysteresis characteristics. 12. A system of claim 1 adapted to: (i) setting a clock frequency of at least a part of the multiprocessor system to a value in accordance with a first processor load, the value being less than a maximum value;(ii) subsequently increasing the clock frequency of the at least the part of the multiprocessor system to a maximum in accordance with a second processor load; and(iii) subsequently reducing the clock frequency of the at least the part of the multiprocessor system in accordance with an operating temperature threshold for preventing overtemperature. 13. The system of claim 12 adapted to subsequently reduce the clock frequency in accordance with a hysteresis characteristics. 14. The system of claim 1, wherein a low power operation mode is provided such that a first data processing unit is active while a plurality of other data processing units are deactivated. 15. The system of claim 14, wherein the first data processing unit is adapted to activate at least some of the other data processing units for data processing in response to an event. 16. The system of claim 1, wherein in the low power mode the minimum clock rate of the plurality of other units is set in accordance clock rate necessary for preserving the memory contents. 17. The system of claim 1 adapted to selectively set the clock frequency of at least some of the processing units in response to a prioritization of a task assigned. 18. The system of claim 1, wherein the plurality of data processing units are disposed within a mobile device. 19. A mobile device comprising: a multiprocessor system including: a plurality of data processing units, each of the data processing units: (a) being programmable; and(b) being adaptable for sequentially processing data in a clocked manner; and including(c1) at least one Arithmetic Logic Unit (ALU), and(c2) at least one data register set for storing intermediate results in sequential data processing;at least one bus system for at least interconnecting at least some of the data processing units, each of the data processing units being provided a supply voltage by a voltage supply;wherein for at least some of the data processing units, the clock frequency is adjustable at runtime without affecting the clock frequency of at least one of: one other of the data processing units and the bus system; andwherein the voltage supply is adapted to supply higher supply voltages for data processing at higher clock frequencies. 20. The mobile device of claim 19 further comprising a battery. 21. The mobile device of claim 20 further comprising a heat sink for the multiprocessor system. 22. The mobile device of claim 19, wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to a priority of a sequential task. 23. The mobile device of claim 22, wherein the processor is adapted to reduce the supply voltage when the clock frequency is reduced. 24. The mobile device of claim 23 further comprising: a heterogeneous plurality of clocked data processing units. 25. The mobile device according to claim 20 further comprising: a plurality of temperature sensors and a heterogeneous plurality of clocked data processing units,the multiprocessor having a plurality of regions, a temperature sensor being provided for each of said plurality of regions to measure the temperature of said specific region; andthe clock frequencies of said data processing units being dynamically adjustable in accordance with the sensed temperatures. 26. The mobile device according to claim 20 adapted to: (i) setting a clock frequency of at least a part of the multiprocessor system to a value in accordance with a first processor load, the value being less than a maximum value;(ii) subsequently increasing the clock frequency of the at least the part of the multiprocessor system to a maximum in accordance with a second processor load; and(iii) subsequently reducing the clock frequency of the at least the part of the multiprocessor system in accordance with an operating temperature threshold for preventing overtemperature. 27. The mobile device according to claim 20 adapted to subsequently reduce the clock frequency in accordance with a hysteresis characteristics. 28. The mobile device according to claim 20, wherein a low power operation mode is provided such that a first data processing unit is active while a plurality of other units are deactivated. 29. The mobile device of claim 28, wherein the first entity is adapted to activate at least some of the other units for data processing in response to an event. 30. The mobile device of claim 28, wherein in the low power mode the minimum clock rate of the plurality of other units is set in accordance clock rate necessary for preserving the memory contents. 31. The mobile device of according to claim 20 adapted to selectively set the clock frequency of at least some of the processing units in response to a prioritization of a task assigned. 32. The mobile device of claim 19 wherein for at least some of the data processing units, the clock frequency is adjustable at runtime according to at least one of: a state of the multiprocessor system, a state of the data processing entity, a state of others of the data processing units, and a priority of a sequential task. 33. The mobile device according to claim 20 wherein the mobile device is a mobile computer. 34. A method of operating a multiprocessor system, the multiprocessor system comprising: a plurality of programmable data processing units, each including at least one Arithmetic Logic Unit (ALU), andat least one data register set for storing intermediate results for sequential data processing;the method comprising:sequentially processing data in a clocked manner via the plurality of programmable data processing units;interconnecting at least some of the data processing units via at least one bus system;supplying to at least some of the data processing units a supply voltage from a voltage supply; andfor at least some of the data processing units:adjusting a clock frequency at runtime, without affecting the clock frequency of at least one of: one other of the data processing units and the bus system; andsupplying higher supply voltage for data processing at higher clock frequencies. 35. The method of claim 34, wherein the adjusting the clock frequency at runtime is adjusted according to a state of the multiprocessor system. 36. The method of claim 34, wherein the adjusting the clock frequency at runtime is adjusted according to a state of a least one data processing unit. 37. The method of claim 34, wherein the adjusting the clock frequency at runtime is adjusted according to a state of others data processing units. 38. The method of claim 34, wherein the adjusting the clock frequency at runtime is adjusted according to a priority of a sequential task. 39. The method according to claim 34, wherein the clock rate is set in response to an amount of data buffered for processing. 40. The method according to claim 34, wherein the clock rate is set in response to an increase rate of an amount of data buffered for processing. 41. The method according to claim 34, wherein the clock rate is set in response to a decrease rate of an amount of data buffered for processing. 42. The method according to claim 34, wherein the clock rate is set in response to a release condition for execution. 43. The method according to claim 34, wherein the clock rate is set in response to a hysteresis behavior. 44. The method according to claim 34, wherein the clock rate is set in response to one or more measured temperatures. 45. The method according to claim 34, wherein the clock rate is set in response to an overtemperature condition.
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Songer, Christopher Mark; Konas, Pavlos; Gauthier, Marc E.; Chea, Kevin C., Abstraction of configurable processor functionality for operating systems portability.
Chin Danny (West Windsor Township NJ) Peters ; Jr. Joseph E. (East Brunswick NJ) Taylor ; Jr. Herbert H. (Hopewell Township NJ), Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to inc.
Robinson Jeffrey I. (New Fairfield CT) Rouse Keith (Lebanon NJ) Krassowski Andrew J. (Long Valley NJ) Montlick Terry F. (Bethlehem CT), Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tas.
Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX), Array processor communication architecture with broadcast processor instructions.
Wang,Albert Ren Rui; Ruddell,Richard; Goodwin,David William; Killian,Earl A.; Bhattacharyya,Nupur; Medina,Marines Puig; Lichtenstein,Walter David; Konas,Pavlos; Srinivasan,Rangarajan; Songer,Christop, Automated processor generation system for designing a configurable processor and method for the same.
Goetting F. Erich (Cupertino CA) Parlour David B. (Pittsburgh PA) Trimberger Stephen M. (San Jose CA), Compact logic cell for field programmable gate array chip.
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
Sluijter Robert J. (Eindhoven NLX) Huizer Cornelis M. (Eindhoven NLX) Dijkstra Hendrik (Eindhoven CA NLX) Slavenburg Gerrit A. (Sunnyvale CA), Data processing module and video processing system incorporating same.
Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Furtek Frederick (Menlo Park CA), Diagonal wiring between abutting logic cells in a configurable logic array.
Angle Richard L. ; Harriman ; Jr. Edward S. ; Ladwig Geoffrey B., Distributed pipeline memory architecture for a computer system with even and odd pids.
Pechanek Gerald G. ; Larsen Larry D. ; Glossner Clair John ; Vassiliaadis Stamatis,NLX, Distributed processing array with component processors performing customized interpretation of instructions.
DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Hartmann Alfred C., Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip.
Hiller John (New York NY) Johnsen Howard (Granite Spring NY) Mason John (Ramsey NJ) Mulhearn Brian (Paterson NJ) Petzinger John (Oakland NJ) Rosal Joseph (Bronx NY) Satta John (White Plains NY) Shurk, Highly parallel computer architecture employing crossbar switch with selectable pipeline delay.
Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
Shams Soheil ; Shu David B., Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same.
Takano, Hiroyuki, Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions.
Evan Shabtai (Saratoga CA) Sander Wendell B. (Los Gatos CA), Input/output section for an intelligent cell which provides sensing, bidirectional communications and control.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Logic system of logic networks with programmable selected functions and programmable operational controls.
Van Doren Stephen R. ; Steely ; Jr. Simon C. ; Gharachorloo Kourosh ; Sharma Madhumitra, Mechanism for optimizing generation of commit-signals in a distributed shared-memory system.
Steely ; Jr. Simon C. ; Sharma Madhumitra ; Van Doren Stephen R. ; Gharachorloo Kourosh, Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches.
Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.
Kundu Aniruddha ; Khandekar Narendra, Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic.
Razdan Rahul ; Webb ; Jr. David Arthur James ; Keller James ; Meyer Derrick R. ; Leibholz Daniel Lawrence, Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol.
Sharma Madhumitra ; Van Doren Stephen R. ; Gharachorloo Kourosh ; Steely ; Jr. Simon C., Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system.
Borkenhagen John Michael ; Eickemeyer Richard James ; Flynn William Thomas ; Wottreng Andrew Henry, Method and apparatus to force a thread switch in a multithreaded processor.
Kahle James A. ; Mallick Soummya ; McDonald Robert G., Method and system for constructing a program including out-of-order threads and processor and method for executing threa.
Jones Michael B. ; Leach Paul J. ; Draves ; Jr. Richard P. ; Barrera ; III Joseph S. ; Levi Steven P. ; Rashid Richard F. ; Fitzgerald Robert P., Method and system for scheduling the execution of threads using optional time-specific scheduling constraints.
Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
Cooke, Laurence H.; Phillips, Christopher E.; Wong, Dale, Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic.
Dean Jeffrey A. ; Waldspurger Carl A., Method for estimating statistics of properties of memory system interactions among contexts in a computer system.
Ekanadham Kattamuri ; Moreira Jose Eduardo ; Naik Vijay Krishnarao, Method for resource control in parallel environments using program organization and run-time support.
Ekanadham Kattamuri ; Moreira Jose Eduardo ; Naik Vijay Krishnarao, Method for resource control in parallel environments using program organization and run-time support.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
Bruce Richard H. (Los Altos CA) Gastinel Jean (Palo Alto CA) Gunning William F. (Los Altos Hills CA) Overton Michael (Palo Alto CA), Multi-segmented bus and method of operation.
Arimilli, Ravi Kumar; Dodson, John Steven; Guthrie, Guy Lynn, Multiprocessor computer system with sectored cache line mechanism for cache intervention.
Takahashi Hajime,JPX ; Hattori Nobuhisa,JPX ; Tsuzuki Toshihide,JPX ; Funaki Jun,JPX, Multiprocessor system connected by a duplicated system bus having a bus status notification line.
Foster David J. (White Plains NY) Garcia Armando (Yorktown Heights NY) Pearson Robert B. (Cold Spring NY), Multiprocessor system having local write cache within each data processor node.
Holsztynski Wlodzimierz (Mountainview CA) Benton Richard W. (Altamonte Springs FL) Johnson W. Keith (Goleta CA) McNamara Robert A. (Orlando FL) Naeyaert Roger S. (Plano TX) Noden Douglas A. (Orlando , Parallel data processor.
Hillis W. Daniel (Brookline MA), Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and.
Butts Michael R. (Portland OR) Batcheller Jon A. (Newburg OR), Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logi.
Garnett Paul J.,GBX ; Rowlinson Stephen,GBX ; Oyelakin Femi A.,GBX ; Williams Emrys J., Processor bridge with dissimilar data registers which is operable to disregard data differences for dissimilar data write accesses.
Bertolet Allan Robert (Williston VT) Ferguson Kenneth (Edinburgh GB6) Gould Scott Whitney (South Burlington VT) Millham Eric Ernest (St. George VT) Palmer Ronald Raymond (Westford VT) Worth Brian (Mi, Programmable array I/O-routing resource.
Gould Scott Whitney (South Burlington VT) Furtek Frederick Curtis (Menlo Park CA) Keyser ; III Frank Ray (Colchester VT) Worth Brian A. (Milton VT) Zittritsch Terrance John (Williston VT), Programmable array clock/reset resource.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
Bertolet Allan Robert (Williston VT) Clinton Kim P. N. (Essex Junction VT) Fuller Christine Marie (Williston VT) Gould Scott Whitney (South Burlington VT) Hartman Steven Paul (Jericho VT) Iadanza Jos, Programmable logic cell having configurable gates and multiplexers.
Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Hung, Ching-Yu; Estevez, Leonardo W.; Rabadi, Wissam A., Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing).
Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).
MacWilliams Peter D. (Aloha OR) Rasmussen Norman J. (Hillsboro OR) Wade Nicholas D. (Vancouver WA) Wu William S. F. (Cupertino CA), Scalable cache attributes for an input/output bus.
Michael Ignatowski ; Thomas James Heller, Jr. ; Gottfried Andreas Goldiran DE, Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls.
Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX) McCabe Daniel H. (Chapel Hill NC), Selective processing and routing of results among processors controlled by decoding instructions using mask value derive.
Lua, Edmund Koon Tian; Leow, See Hiong; Lee, Choon Kuan, Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices.
Larson Ronald J. (Minneapolis MN), State machine having a variable timing mechanism for varying the duration of logical output states of the state machine.
Rubinstein Jon (Palo Alto CA) Klingman Kenneth C. (Portola CA), System for assigning interrupts to least busy processor that already loaded same class of interrupt routines.
Webb Charles Franklin ; Bair Dean G. ; Farrell Mark Steven ; Krumm Barry Watson ; Mak Pak-kin ; Navarro Jennifer Almoradie ; Slegel Timothy John, System serialization with early release of individual processor.
Sluijter Robert J. (Eindhoven NLX) Huizer Cornelis M. (Eindhoven NLX) Dijkstra Hendrik (Eindhoven NLX), System with plurality of processing elememts each generates respective instruction based upon portions of individual wor.
Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
Garverick Tim (Cupertino CA) Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Smith ; Jr. Arthur (San Carlos CA) Pickett Scott (Los Gatos CA) Hawley David (Belm, Versatile and efficient cell-to-local bus interface in a configurable logic array.
Schmidt Ulrich (Freiburg DEX) Caesar Knut (Gundelfingen DEX), Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake.
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