초록 ▼

An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an oper

An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an operation step of applying the type of operation to an N*M-bit provisional operand that is formed by concatenating the N M-bit operands, to obtain one N*M-bit provisional operation result, and generating correction information based on an effect had, by applying the operation, on each M bits of the provisional operation result from a bit that neighbors the M bits; and a correction step of correcting the provisional operation result in M-bit units with use of the correction information, to obtain the N M-bit operation results.

대표청구항 ▼

1. An operation method for having an operation apparatus execute (a) an existing operation that applies a predetermined type of operation to one N*M-bit first-bit-length operand, to obtain one N*M-bit first-bit length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation use

1. An operation method for having an operation apparatus execute (a) an existing operation that applies a predetermined type of operation to one N*M-bit first-bit-length operand, to obtain one N*M-bit first-bit length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation used for applying N parallel operations that applies the predetermined type of operation in parallel to N M-bit second-bit-length operands to obtain N M-bit second-bit-length operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1, the operation apparatus implementing:an operation instruction for instructing application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; andan SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation,the operation apparatus comprising:a storage unit storing the first-bit-length operation result, and correction information that is used in the correction:the operation method comprising:a decoding step of decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; andan execution step of,(e) when the operation instruction is decoded, applying the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit length operands concatenated and considered to be a first-bit-length operand, to obtain one first-bit-length operation result, storing the obtained first-bit-length operation result in the storage unit, and generating correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the first-bit-length operation result from a bit that neighbors the M bits, and storing the generated correction information in the storage unit, and(f) when the SIMD correction instruction used for applying N parallel operations is decoded, correcting the stored first-bit-length operation result in M-bit units using the stored correction information, to obtain the N second-bit-length operation results,wherein when executing the existing instruction, the operation instruction is decoded and an obtained first-bit-length operation result is considered to be an operation result of the existing operation, andwhen executing the SIMD operation, the operation instruction is decoded, an obtained first-bit-length operation result is considered to be a provisional operation result, the SIMD operation is then decoded, and N second-bit-length operation results obtained by correcting the provisional operation result are considered to be an operation result of the SIMD operation. 2. The operation method of claim 1, wherein in the execution step, when the SIMD correction instruction used for applying N parallel operations is decoded, M least; significant bits of the first-bit-length operation result are excluded from being corrected. 3. The operation method of claim 1, wherein the execution apparatus further executes the SIMD operation used for applying N/P parallel operations that applies the same predetermined type of operation in parallel to N/P M*P-bit third-bit-length operands to obtain N/P M*P-bit third-bit-length operation results, P being an integer equal to or greater than 2 and equal to or less than N/2, the decoding step further decodes the SIMD correction instruction used for applying N/P parallel operations, andthe execution step,(a) when the operation instruction is decoded, applies the predetermined type of operation to the first-bit-length operand, the first-bit-length operand being one of (i) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, and (ii) the N/P third-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain a first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit, generates the correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the first bit-length operation result from a bit that neighbors the M bits, and stores the generated correction information in the storage unit, and(b) when the SIMD operation used for applying N/P parallel operations is decoded, corrects the stored first-bit-length operation result in M*P-bit units, using only parts of the stored correction information that correspond to an effect on each M*P-bit unit. 4. The operation method of claim 3, wherein respective values of N, M and P are one of (a) N=8, M=8 and P=one of (i) 2, (ii) 4, and (iii) 2 and 4, and (b) N=4, M=16 and P=2. 5. The operation method of claim 1, wherein the predetermined type of operation is any one of a plurality of types of operations,the execution step, when a least significant bit is considered to be a first bit,(a) when the operation instruction is decoded, generates the correction information, in M-bit units, based on the predetermined type of operation and a carry from an M*L-th bit to an M*L1-th bit according to the predetermined type of operation, the M*L+1-th bit having a value of one of(a) 0 or 1 and (b) 0 or −1, L being N integers from 0 to N−1, and(b) when the SIMD correction instruction is decoded, performs, regardless of the predetermined type of the operation, one of (a) adding the stored correction information to the first-bit-length operation result in M-bit units, and (b) subtracting the correction information from the first-bit-length operation result in M-bit units, to obtain the NM-bit operation results. 6. The operation method of claim 5, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract,the execution step, (a) when the operation instruction is decoded and the predetermined type is increment, increments the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value −1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information,(b) when the operation instruction is decoded and the predetermined type is decrement, decrements the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,(c) when the operation instruction is decoded and the predetermined type is dyadic add, adds a first first-bit-length operand and a second first-bit-length operand to obtain first-bit-length operation result, the first first-bit-length operand being formed by concatenating N second-bit-length operands, and the second first-bit-length operand being formed by concatenating N second-bit-length operands, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,(d) when the operation instruction is decoded and the predetermined type is dyadic subtract, subtracts a second first-bit-length operand from a first first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N second-bit-length operands, and the second first-bit-length operand being formed by concatenating N second-bit-length operands, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value −1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information, and(e) when the SIMD correction instruction is decoded, subtracts, in M-bit units, the stored correction information from the first-bit-length operation result, to obtain the N second-bit-length operation results. 7. The operation method of claim 5, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract,the execution step, (a) when the operation instruction is decoded and the predetermined type is increment, increments the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information,(b) when the operation instruction is decoded and the predetermined type is decrement, decrements the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1-th bit position with a carry according to the operation being represented by a value −1 in the correction information,(c) when the operation instruction is decoded and the predetermined type is dyadic add, adds a first first-bit-length operand and a second first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N second-bit-length operands, and the second first-bit-length operand being formed by concatenating N second-bit-length operands, and generates the correction information, each represented by a value 0 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value −1 in the correction information, and(d) when the operation instruction is decoded and the predetermined type is dyadic subtract, subtracts the second first-bit-length operand from the first first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N first-bit-length operands, and the second first-bit-length operand being formed by concatenating N second-bit-length operands, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information, andwhen the SIMD correction instruction for N parallel operations is decoded, subtracts, in M-bit units, the stored correction information from the stored first-bit-length operation result, to obtain the N second-bit-length operation results. 8. The operation method of claim 1, wherein the predetermined type of operation is any one of a plurality of types of operations,the execution step further stores type information showing the type, andwhen the SIMD correction instruction used for applying N parallel operations is decoded, corrects the first-bit-length operation result according to the stored type information. 9. The operation method of claim 8, wherein when the operation instruction is decoded, the execution step generates, as the correction information, information showing whether there is a carry from lower bits to corresponding higher bits. 10. The operation method of claim 9, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract,the execution step, in order to obtain the N second-bit-length operation results, where L is N integers from 0 to N−1, and when a least significant bit is considered to be a first bit,(a) when the stored type information shows one of increment and dyadic add, adds 1 to each M*L+1-th bit without a carry in the provisional operation result, based on the generated correction information, and(b) when the stored type information shows one of decrement and dyadic subtract, subtracts 1 from each M*L+1-th bit with a carry in the provisional calculation result, based on the generated correction information. 11. An operation method for having an operation apparatus execute (a) an existing operation that applies a predetermined type of operation to a first-bit-length operand, to obtain one first-bit-length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation used for applying N parallel operations that applies a predetermined type of operation in parallel to N second-bit-length operands to obtain N second-bit-length operation results, N being an integer equal to or greater than 2, the operation apparatus implementing: an operation instruction for instruction application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; andan SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation, andthe operation apparatus comprising:a storage unit storing the first-bit-length operation result, and correction information that is used in the correction, andthe operation method comprising:a decoding step of decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; andan execution step of,(e) when the operation instruction is decoded, applying the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain one first-bit-length operation result, storing the obtained first-bit-length operation result in the storage unit, and generating correction information that corresponds to a difference between the first-bit-length operation result and a first-bit-length operation result that is the N second-bit-length operation results concatenated, and store the generated correction information in the storage unit, and(f) when the SIMD correction instruction used for applying N parallel operations is decoded, correcting the stored first-bit-length operation result using the stored correction information, to obtain the N second-bit-length operation results,wherein when executing the existing instruction, the operation instruction is decoded and an obtained first-bit-length operation result is considered to be an operation result of the existing operation, andwhen executing the SIMD operation, the operation instruction is decoded, an obtained first-bit-length operation result is considered to be a provisional operation result, the SIMD operation is then decoded, and N second-bit-length operation results obtained by correcting the provisional operation result are considered to be an operation result of the SIMD operation. 12. The operation method of claim 11, wherein when M is an integer equal to or greater than 1, the first-bit-length operand is N*M bits in length, each second-bit-length operand is M bits in length, and each second-bit-length operation result is M*2 bits in length,the execution step applies the predetermined type of operation to one of (a) the first-bit-length operand and (b) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain the N*M*2-bit first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit, generates correction information based on an effect had, by applying the operation, on each M*2 bits of the first-bit-length operation result from another M*2 bits, and stores the generated correction information in the storage unit. 13. The operation method computer readable medium of claim 12, further having the execution apparatus execute the SIMD operation used for applying N/P parallel operations that applies the same predetermined type of operation in parallel to N/P M*P-bit third-bit-length operands, to obtain N/P M*P*2-bit third-bit-length operation results, P being an integer equal to or greater than 2 and equal to or less than N/2, wherein the decoding step further decodes the SIMD correction instruction used for applying N/P parallel operations,the execution step, (a) when the operation instruction is decoded, applies the predetermined type of operation to the first-bit-length operand, the first-bit-length operand being one of (i) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, and (ii) the N/P third-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain one N*M*2-bit first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit,where L is N−1 integers from 0 to N−1 and when a least significant bit is considered to be a first bit, generates first correction information, for each M*2 bits, based N−1 effects by the type of operation between (iii) the M*2*L-th bit and lower bits and (iv) the M*2*L+1 bit position and higher bits, and generates second correction information, for each M*2*P bits, based on N/P−1 effects by the type of operation between (v) the M*2*P*L-th bit and lower bits and (vi) the M*2*L+1-th bit and higher bits, and stores the first correction information and second correction information in the storage unit,(b) when the SIMD correction instruction used for applying N parallel operations is decoded, corrects the stored first-bit-length operation result with use of the stored first correction information, and(c) when the SIMD correction instruction used for applying N/P parallel operations is decoded, corrects the first-bit-length operation result with use of the stored second correction information. 14. The operation method of claim 13, wherein N=8, M−=4M=4, P=2, and the predetermined type of operation is multiply. 15. An operation apparatus that when N is an integer equal to or greater than 2, and M is an integer equal to or greater than 1, executes (a) an existing operation that applies a predetermined type of operation to one N*M-bit first-bit-length operand, to obtain one N*M-bit first-bit-length operation result, and (b) an SIMD (Single Instruction Multiple Data) that applies a predetermined type of operation in parallel to N M-bit second-bit -length second operands, to obtain NM-bitN M-bit second-bit-length operation results,the operation apparatus implementing:an operation instruction for instructing application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; andan SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation, andthe operation apparatus comprising:a storage unit storing the first-bit-length operation result, and correction information that is used in the correction;a decoding unit decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; andan execution unit,(e) when the operation instruction is decoded, applies the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain one MA-bitN*M-bit first-bit-length operation result, store the obtained NW-bitN*M-bit first-bit-length operation result in the storage unit, and generate correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the N*M-bit first-bit-length operation result from a bit that neighbors the M bits, and store the generated correction information in the storage unit, and(f) when the SIMD correction instruction used for applying N parallel operations is decoded, to correct the stored first-bit-length operation result in M-bit units using the stored correction information, to obtain the N second-bit-length operation results. 16. The operation apparatus of claim 15, wherein the execution unit, when the SIMD correction instruction used for applying N parallel operations is decoded, excludes M least significant bits of the first-bit-length operation result from being corrected. 17. The operation apparatus of claim 15, further executing the SIMD operation used for applying N/P parallel operations that applies the same predetermined type of operation in parallel to N/P M*P-bit third-bit-length operands, to obtain N/P M*P-bit third-bit-length operation results, P being an integer equal to or greater than 2 and equal to or less than N/2, wherein the decoding unit further decodes the SIMD correction instruction used for applying N/P parallel operations, and the execution unit,(a) when the operation instruction is decoded, applies the predetermined type of operation to the first-bit-length operand, the first bit-length operand being one of (i) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, and (ii) the N/P third-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain a first-bit -length operation result, stores the obtained first-bit-length operation result in the storage unit, generates the correction information based on an effect had, by applying the operation, on each M bits of-the first bit-length operation result from a bit that neighbors the M bits, and stores the generated correction information in the storage unit, and(b) when the SIMD operation used for applying N/P parallel operations is decoded, corrects the stored first-bit-length operation result in M*P-bit units, using only parts of the stored correction information that correspond to an effect on each M*P-bit unit. 18. The operation apparatus of claim 17wherein respective values of N, M and P are one of (a) N=8, M=8 and P=one of (i) 2, (ii) 4, and (iii) 2 and 4, and (b) N−=4N=4, M=16 and P=2. 19. The operation apparatus of claim 15, wherein the type of operation is any one of a plurality of types of operations, andthe execution unit, where L is N integers from 0 to N−1, when a least significant bit is considered to be a first bit, and when the operation instruction is decoded, generates correction information, in M-bit units, based on the type of operation and a carry from an M*L-th bit to an M*L+1-th bit according to the operation, the correction information showing for M bits the value of the M*L+1-th as one of (a) 0 or 1 and (b) 0 or −1, and when the SIMD correction instruction is decoded, performs, regardless of the type of the operation, one of (a) adding the stored correction information to the first-bit-length operation result in M-bit units, and (b) subtracting the correction information from the first-bit-length operation result in M-bit units. 20. The operation apparatus of claim 19, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract, andthe execution unit (a) when the operation instruction is decoded and the predetermined type is increment, increments the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value −1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information,(b) when the operation instruction is decoded and the predetermined type is decrement, decrements the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1thM*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,(c) when the operation instruction is decoded and the predetermined type is dyadic add, adds a first first-bit-length operand and a second first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N M-bit operands, and the second first-bit-length operand being formed by concatenating N M-bit operands, and generates correction information, each M*L+1-th without a carry according to the operation being represented by a value 0 in the correction information, and M*L+1-th bit with a carry according to the operation being represented by a value 1 in the correction information,(d) when the operation instruction is decoded and the predetermined type is dyadic subtract, subtracts a second first-bit-length operand from a first first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N M-bit operands, and the second first bit-length operand being formed by concatenating N M-bit operands, and generates correction information, each M*L+1-th bit without a carry according to the operation being represented by a value −1 in the correction information, and each M*L+1-th bit position with a carry according to the operation being represented by a value 0 in the correction information, and(e) when the SIMD correction instruction is decoded, subtracts, in M-bit units, the stored correction information from the stored first-bit-length operation result, to obtain the N second-bit-length operation results. 21. The operation apparatus of claim 19, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract, andthe execution unit (a) when the, operation instruction is decoded and the predetermined type is increment, increments the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 1 in the correction information, and each M*L+1-th bit with a carry according to the operation being represented by a value 0 in the correction information,(b) when the operation instruction is decoded and the predetermined type is decrement, decrements the first-bit-length operand, to obtain a first-bit-length operation result, and generates the correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and each M*L+1thM*L+1-th bit with a carry according to the operation being represented by a value −1 in the correction information,(c) when the operation instruction is decoded and the predetermined type is dyadic add, adds a first first-bit-length operand and a second first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N M-bit operands, and the second first-bit-length operand being formed by concatenating N M-bit operands, and generates correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 0 in the correction information, and M*L+1-th bit with a carry according to the operation being represented by a value −1 in the correction information,(d) when the operation instruction is decoded and the predetermined type is dyadic subtract, subtracts a second first-bit-length operand from a first first-bit-length operand to obtain a first-bit-length operation result, the first first-bit-length operand being formed by concatenating N M-bit operands, and the second first bit-length operand being formed by concatenating IV h-bitN M-bit operands, and generates correction information, each M*L+1-th bit without a carry according to the operation being represented by a value 1, and each M*L+1-th bit position with a carry according to the operation being represented by a value 0 in the correction information, and(e) when the SIMD correction instruction for N parallel operations is decoded, subtracts, in M-bit units, the stored correction information from the stored first-bit-length operation result, to obtain the N second-bit-length operation results. 22. The operation apparatus of claim 15, wherein the type of operation is any one of a plurality of types of operations,the execution unit further stores type information showing the predetermined type, and, when the SIMD correction instruction used for applying N parallel operations is decoded, corrects the stored first-bit-length operation result according to the stored type. 23. The operation apparatus of claim 22, wherein, when the operation instruction is decoded, the execution unit generates, as the correction information, information showing whether there is a carry from lower bits to corresponding higher bits. 24. The operation apparatus of claim 23, wherein the plurality of types of operations includes at least one of increment, decrement, dyadic add, and dyadic subtract,the execution unit, in order to obtain the N M-bit operation results, where L is N integers from 0 to N−1, and when a least significant bit is considered to be a first bit,(a) when the stored type information shows one of increment and dyadic add, adds 1 to each M*L+1-th bit without a carry in the provisional operation result, based on the generated correction information, and(b) when the stored type information shows one of decrement and dyadic subtract, subtracts 1 from each M*L+1-th bit with a carry in the provisional calculation result, based on the generated correction information. 25. The operation apparatus of claim 22, farther comprising: a saving unit when an interrupt is received or when switching to another context, saving contents stored in the storage unit to a storage apparatus that is external to the operation apparatus; anda restoration unit when returning from the interrupt or switching back to an original context, restoring the saved contents to the storage unit. 26. The operation apparatus of claim 15, further comprising: a saving unit when an interrupt is received or when switching to another context, saving contents stored in the storage unit to a storage apparatus that is external to the operation apparatus; anda restoration unit when returning from the interrupt or switching back to an original context, restoring the saved contents to the storage unit. 27. An operation apparatus that executes (a) an existing operation that applies a predetermined type of operation to a first-bit-length operand, to obtain one first-bit-length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation used for applying N parallel operations that applies a predetermined type of operation in parallel to N second-bit-length operands, to obtain N second-bit-length operation results, N being an integer equal to or greater than 2, the operation apparatus implementing:an operation instruction for instructing application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; andan SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation, andthe operation apparatus comprising:a storage unit storing the first-bit-length operation result, and correction information that is used in the correction;a decoding unit decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; andan execution unit,(e) when the operation instruction is decoded, applying the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain a first first-bit-length operation result, store the obtained first first-bit-length operation result in the storage unit, and generate correction information that corresponds to a difference between the first first-bit-length operation result and a second first-bit-length operation result that is the N second-bit-length operation results concatenated, and store the generated correction information in the storage unit, and(f) when the SIMD correction instruction for applying N parallel operations is decoded, to correct the stored first first-bit-length operation result using the stored correction information, to obtain N SIMD operation second bit-length operation results. 28. The operation apparatus of claim 27, wherein, when M is an integer equal to or greater than 1, the first-bit-length operand is N*M bits in length, each second-bit-length operand is M bits, the first first-bit-length operation result is N*M*2 bits in length, and each second-bit-length operation result is M*2 bits in length, andthe execution unit applies the predetermined type of operation to one of (a) the first-bit-length operand and (b) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain an N*M*2-bit first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit, generates correction information based on an effect had, by applying the predetermined type of operation, on each M*2 bits of the first-bit-length operation result, from other M*2 bits, and stores the correction information in the storage unit. 29. The operation apparatus of claim 28, further executing the SIMD operation used for applying N/P parallel operations that applies the same predetermined type of operation in parallel to N/P, M*P-bit third-bit-length operands, to obtain N/P M*P*2-bit third-bit-length operation results, P being an integer equal to or greater than 2 and equal to or less than N/2, wherein the decoding unit further decodes the SIMD correction instruction used for applying N/P parallel operations,the execution unit, (a) when the operation instruction is decoded, applies the predetermined type of operation to the first-bit-length operand, the first-bit-length operand being one of (i) the N second-bit-length operands concatenated and considered to be a first-bit-length operand, and (ii) the N/P third-bit-length operands concatenated and considered to be a first-bit-length operand, to obtain one N*M*2-bit first-bit-length operation result, stores the obtained first-bit-length operation result in the storage unit,where L is N−1 integers from 0 to N−1, and when a least significant bit is considered to be a first bit, generates first correction information, for each M*2 bits, based N−1 effects by the predetermined type of operation between (iii) the M*2*L-th bit and lower bits and (iv) the M*2*L+1-th bit position and higher bits, and generates second correction information, for each M*2*P bits, based on N/P−1 effects by the predetermined type of operation between (v) the M*2*P*L-th bit and lower bits and (vi) the M*2*L+1-th bit and higher bits, and stores the first correction information and second correction information in the storage unit,(b) when the SIMD correction instruction used for applying N parallel operations is decoded, corrects the stored first-bit-length operation result with use of the stored first correction information, and(c) when the SIMD correction instruction used for applying N/P parallel operations is decoded, corrects the stored first-bit-length operation result with use of the stored second correction information. 30. The operation apparatus of claim 29, wherein N=8, M=4, P=2, and the type of operation is multiply. 31. The operation apparatus of claim 27, further comprising: a saving unit when an interrupt is received or when switching to another context, saving contents stored in the storage unit to a storage apparatus that is external to the operation apparatus; anda restoration unit when returning from the interrupt or switching back to an original context, restoring the saved contents to the storage unit. 32. An SIMD (Single Instruction Multiple Data) processor that executes N operations for applying a same type of operation in parallel to N M-bit operands to obtain N operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1, the SIMD operation apparatus implementing:an instruction set which includes an SIMD decrementing instruction for subtracting a value of one from each of the N M-bit operands regardless of values of the N M-bit operands,wherein the value of one is not designated by any operand in the SIMD decrementing instruction,wherein in subtracting the value of one from each of the N M-bit operands by the SIMD decrementing instruction, no carry is propagated from each M*L-th bit to corresponding M*L+1-th bit, L being an integer from 1 to N−1 and an LSB (least significant bit) being considered to be a first bit position, andwherein subtracting the value of one from each of the N M-bit operands is performed by adding a value of minus one to each of the N M-bit operands. 33. The SIMD processor of claim 32, comprising: a decoding unit for decoding the SIMD decrementing instruction; andan execution unit, when the decoding unit decodes the SIMD decrementing instruction, for subtracting the value of one from each of N M-bit operands designated by the SIMD decrementing instruction. 34. The SIMD processor of claim 33, wherein the SIMD decrementing instruction is designated in a software program. 35. The SIMD processor of claim 32, wherein the SIMD decrementing instruction is designated in a software program. 36. The SIMD processor of claim 32, wherein the SIMD decrementing instruction is: (a) an instruction for decrementing each value of N pieces of 8-bit data in the operands in parallel,(b) an instruction for decrementing each value of N pieces of 16-bit data in the operands in parallel,(c) an instruction for decrementing each value of N pieces of 32-bit data in the operands in parallel, or(d) an instruction for decrementing each value of N pieces of 64-bit data in the operands in parallel. 37. The SIMD processor of claim 32, wherein: the instruction set further includes an SIMD subtraction instruction, andthe SIMD decrementing instruction and the SIMD subtraction instruction are different from each other. 38. The SIMD processor of claim 32, wherein the SIMD processor is a microprocessor composed on a single semiconductor chip. 39. An SIMD (Single Instruction Multiple Data) processor that executes N operations for applying a same type of operation in parallel to N M-bit operands to obtain N operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1, the SIMD processor implementing:an instruction set which includes an SIMD incrementing instruction for adding an M-bit-one to each of the N M-bit operands,wherein the M-bit-one is a value of one expressed in an M-bit number, andwherein N M-bit-ones are stored in a register. 40. The SIMD processor of claim 39, comprising: a decoding unit for decoding the SIMD incrementing instruction; andan execution unit, when the decoding unit decodes the SIMD incrementing instruction, for adding the M-bit-one to each of the N M-bit operands designated by the SIMD incrementing instruction. 41. The SIMD processor of claim 40, wherein the SIMD incrementing instruction is designated in a software program. 42. The SIMD processor of claim 39, wherein in adding the M-bit-one to each of the N M-bit operands by the SIMD incrementing instruction, no carry is propagated from each M*L-th bit to corresponding M*L+1-th bit, L being an integer from 1 to N−1 and an LSB (least significant bit) being considered to be a first bit position. 43. The SIMD processor of claim 39, wherein the SIMD incrementing instruction is designated in a software program. 44. The SIMD processor of claim 39, wherein the SIMD incrementing instruction is: (a) an instruction for incrementing each value of N pieces of 8-bit data in the operands in parallel,(b) an instruction for incrementing each value of N pieces of 16-bit data in the operands in parallel,(c) an instruction for incrementing each value of N pieces of 32-bit data in the operands in parallel, or(d) an instruction for incrementing each value of N pieces of 64-bit data in the operands in parallel. 45. The SIMD processor of claim 39, wherein: the instruction set further includes an SIMD add instruction, andthe SIMD incrementing instruction and the SIMD add instruction are different from each other. 46. An SIMD (Single Instruction Multiple Data) processor that executes N operations for applying a same type of operation in parallel to N M-bit operands to obtain N operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1, the SIMD processor implementing:an instruction set which includes an SIMD decrementing instruction for subtracting an M-bit-one from each of the N M-bit operands,wherein the M-bit-one is a value of one expressed in an M-bit number, andwherein N M-bit-ones are stored in a register. 47. The SIMD processor of claim 46, comprising: a decoding unit for decoding the SIMD decrementing instruction; andan execution unit, when the decoding unit decodes the SIMD decrementing instruction, for subtracting the M-bit-one from each of N M-bit operands designated by the SIMD decrementing instruction. 48. The SIMD processor of claim 47, wherein the SIMD decrementing instruction is designated in a software program. 49. The SIMD processor of claim 46, wherein in subtracting the M-bit-one from each of the N M-bit operands by the SIMD decrementing instruction, no carry is propagated from each M*L-th bit to corresponding M*L+1-th bit, L being an integer from 1 to N−1 and an LSB (least significant bit) being considered to be a first bit position. 50. The SIMD processor of claim 49, wherein subtracting the M-bit-one from each of the N M-bit operands is performed by adding a value of minus one to each of the N M-bit operands. 51. The SIMD processor of claim 46, wherein the SIMD decrementing instruction is designated in a software program. 52. The SIMD processor of claim 46, wherein the SIMD decrementing instruction is: (a) an instruction for decrementing each value of N pieces of 8-bit data in the operands in parallel,(b) an instruction for decrementing each value of N pieces of 16-bit data in the operands in parallel,(c) an instruction for decrementing each value of N pieces of 32-bit data in the operands in parallel, or(d) an instruction for decrementing each value of N pieces of 64-bit data in the operands in parallel. 53. The SIMD processor of claim 46, wherein: the instruction set further includes an SIMD subtraction instruction, andthe SIMD decrementing instruction and the SIMD subtraction instruction are different from each other. 54. An SIMD (Single Instruction Multiple Data) processor that executes (i) N operations for applying a same type of operation in parallel to N M-bit operands to obtain N operation results, and(ii) N/2 operations for applying a same type of operation in parallel to N/2 M*2-bit operands to obtain N/2 operation results,N being an integer equal to or greater than 4 and M being an integer equal to or greater than 1,the SIMD processor implementing an instruction set which includes: (a) a first SIMD incrementing instruction for adding a value of one to each of the N M-bit operands; and(b) a second SIMD incrementing instruction for adding a value of one to each of the N/2 M*2-bit operands,wherein the value of one is not designated by any operand in the first SIMD incrementing instruction and the second SIMD incrementing instruction. 55. The SIMD processor of claim 54, wherein in adding the value of one to each of the N/2 M*2-bit operands by the second SIMD incrementing instruction, no carry is propagated from each M*2*K-th bit to corresponding M*2*K+1-th bit, K being an integer from 1 to N/2−1, whereas a carry propagation from each M*J-th bit to corresponding M*J+1-th bit is performed, J being an odd integer from 1 to N−1. 56. An SIMD (Single Instruction Multiple Data) processor that executes (i) N operations for applying a same type of operation in parallel to N M-bit operands to obtain N operation results, and(ii) N/2 operations for applying a same type of operation in parallel to N/2 M*2-bit operands to obtain N/2 operation results,N being an integer equal to or greater than 4 and M being an integer equal to or greater than 1,the SIMD processor implementing an instruction set which includes: (a) a first SIMD decrementing instruction for subtracting a value of one from each of the N M-bit operands; and(b) a second SIMD decrementing instruction for subtracting a value of one from each of the N/2 M*2-bit operands,wherein the value of one is not designated by any operand in the first SIMD decrementing instruction and the second SIMD decrementing instruction. 57. The SIMD processor of claim 56, wherein in subtracting the value of one from each of the N/2 M*2-bit operands by the second SIMD decrementing instruction, no carry is propagated from each M*2*K-th bit to corresponding M*2*K-th bit, K being an integer from 1 to N/2−1, whereas a carry propagation from each M*J-th bit to corresponding M*J+1-th bit is performed, J being an odd integer from 1 to N−1. 58. The SIMD processor of claim 57, wherein subtracting the value of one from each of the N M-bit operands is performed by adding a value of minus one to each of the N M-bit operands and subtracting the value of one from each of the N/2 M*2-bit operands is performed by adding the value of minus one to each of the N/2 M*2-bit operands.