Device comprising a ductile layer and method of making the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-021/66
G01R-031/26
G01R-031/28
H01L-023/58
H01L-021/768
H01L-023/532
H01L-023/00
H01L-023/522
H01L-023/525
출원번호
US-0093528
(2016-04-07)
등록번호
US-9576867
(2017-02-21)
발명자
/ 주소
Meyer-Berg, Georg
Pufall, Reinhard
출원인 / 주소
Infineon Technologies AG
대리인 / 주소
Slater Matsil, LLP
인용정보
피인용 횟수 :
0인용 특허 :
7
초록▼
Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and
Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.
대표청구항▼
1. A component comprising: a substrate;a first metal line disposed over the substrate;an insulating layer disposed over the first metal line;a second metal line disposed over the insulating layer;a ductile metal layer disposed between the first metal line and the second metal line, wherein the ducti
1. A component comprising: a substrate;a first metal line disposed over the substrate;an insulating layer disposed over the first metal line;a second metal line disposed over the insulating layer;a ductile metal layer disposed between the first metal line and the second metal line, wherein the ductile metal layer is composed of a different metal than the first metal line, and wherein the ductile metal layer comprises tin, indium, or undoped aluminum and the first metal line comprises copper; anda metal barrier layer disposed between the first metal line and the second metal line, wherein the metal barrier layer is disposed directly beneath the second metal line, wherein the ductile metal layer is disposed directly beneath the metal barrier layer, and wherein the insulating layer is disposed directly beneath the ductile metal layer. 2. The component according to claim 1, wherein the second metal line comprises a bond pad, and wherein the ductile metal layer and the metal barrier layer are only disposed in an area below the bond pad. 3. The component according to claim 1, wherein the ductile metal layer comprises tin. 4. The component according to claim 1, wherein the ductile metal layer comprises undoped aluminum. 5. The component according to claim 1, wherein the first metal line is a top metal line of a interconnect metallization structure. 6. The component according to claim 1, further comprising a via disposed between the first metal line and the ductile metal layer, wherein the via extends through the insulating layer to directly contact the second metal line, wherein an area around the via is free of the ductile metal layer and the metal barrier layer. 7. A component comprising: a semiconductor substrate;an interconnect metallization structure disposed on the semiconductor substrate, the interconnect metallization structure comprising a metal line;an insulating layer disposed on the interconnect metallization structure;a bond pad disposed on the insulating layer; anda metal layer between the bond pad and the metal line, wherein a metal of the metal layer is configured to move into a potential crack in the insulating layer, wherein the metal layer is disposed adjacent the bond pad, the component further comprising a metal barrier layer between the metal layer and the bond pad, wherein the metal layer is composed of a different metal than the metal line, and wherein the metal layer comprises tin, indium, or undoped aluminum and the metal line comprises copper. 8. The component according to claim 7, wherein the metal of the metal layer comprises a higher degree of ductility than a metal of the metal line or a metal of the bond pad. 9. The component according to claim 7, wherein the metal of the metal layer comprises tin. 10. The component according to claim 7, wherein the metal of the metal layer comprises undoped aluminum. 11. The component according to claim 7, wherein a metal of the bond pad comprises aluminum, wherein a metal of the metal line comprises copper, and wherein the metal of the metal layer comprises tin. 12. The component according to claim 7, further comprising a via disposed between the metal line and the metal layer, wherein the via extends through the insulating layer to directly contact the bond pad, wherein an area around the via is free of the metal layer and the metal barrier layer. 13. A method for manufacturing a component, the method comprising: forming a top metal line over a substrate;forming an insulating layer over the top metal line;forming a ductile metal layer over the top metal line before or after forming the insulating layer; andforming a bond pad over the ductile metal layer such that the insulating layer is between the ductile metal layer and the bond pad or between the ductile metal layer and the top metal line, wherein the ductile metal layer is composed of a different metal than the top metal line, and wherein the ductile metal layer comprises tin, indium, or undoped aluminum and the top metal line comprises copper. 14. The method according to claim 13, wherein forming the ductile metal layer comprises forming a metal barrier layer on the top metal line, forming the ductile metal layer on the metal barrier layer, and forming the insulating layer on the ductile metal layer. 15. The method according to claim 13, wherein forming the ductile metal layer comprises forming the insulating layer on the top metal line, forming the ductile metal layer on the insulating layer, and forming a metal barrier layer on the ductile metal layer. 16. The method according to claim 13, wherein forming the ductile metal layer comprises forming the ductile metal layer below a bottom surface of the bond pad, wherein an area of the ductile metal layer is about a size of an area of the bottom surface of the bond pad. 17. The method according to claim 13, wherein forming the ductile metal layer comprises forming the ductile metal layer on the entire top metal line. 18. The method according to claim 13, further comprising forming a via in the insulating layer between the top metal line and the metal layer, wherein the via extends through the insulating layer to directly contact the bond pad, wherein an area around the via is free of the ductile metal layer. 19. A method of forming a component comprising: forming a first metal line over a substrate;forming an insulating layer over the first metal line;forming a second metal line over the insulating layer;forming a ductile metal layer between the first metal line and the second metal line, wherein the ductile metal layer is composed of a different metal than the first metal line, and wherein the ductile metal layer comprises tin, indium, or undoped aluminum and the first metal line comprises copper; andforming a metal barrier layer between the first metal line and the second metal line, wherein the metal barrier layer is formed directly beneath the second metal line, wherein the ductile metal layer is formed directly beneath the metal barrier layer, and wherein the insulating layer is formed directly beneath the ductile metal layer. 20. The method according to claim 19, wherein the second metal line comprises a bond pad, and wherein the ductile metal layer and the metal barrier layer are only disposed in an area below the bond pad. 21. The method according to claim 19, further comprising: structuring the ductile metal layer and the metal barrier layer; andforming a via through an opening in the structured ductile metal layer, wherein the via extends from the first metal line through the insulating layer to directly contact the second metal line.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (7)
Mitwalsky Alexander ; Ryan James Gardner, Crack stop formation for high-productivity processes.
Burrell, Lloyd G.; Wong, Kwong H.; Kelly, Adreanne A.; McKnight, Samuel R., Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad.
Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Structures and methods for improving solder bump connections in semiconductor devices.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.