Processes and apparatus for preparing heterostructures with reduced strain by radial distension
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/322
H01L-021/302
H01L-021/687
C30B-025/12
출원번호
US-0142553
(2013-12-27)
등록번호
US-9583363
(2017-02-28)
발명자
/ 주소
Falster, Robert J.
Voronkov, Vladimir V.
Pitney, John A.
Albrecht, Peter D.
출원인 / 주소
SunEdison Semiconductor Limited (UEN201334164H)
대리인 / 주소
Armstrong Teasdale LLP
인용정보
피인용 횟수 :
0인용 특허 :
19
초록
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
대표청구항▼
1. A process for relaxing the strain in a heterostructure comprising a substrate, a surface layer disposed on the substrate and an interface between the substrate and the surface layer, the substrate comprising a central axis, a back surface which is generally perpendicular to the central axis, and
1. A process for relaxing the strain in a heterostructure comprising a substrate, a surface layer disposed on the substrate and an interface between the substrate and the surface layer, the substrate comprising a central axis, a back surface which is generally perpendicular to the central axis, and a diameter extending across the substrate through the central axis, the process comprising: forming a dislocation source layer in the substrate; andsubjecting the dislocation source layer to a stress by radially distending the substrate to generate dislocations and glide the dislocations from the dislocation source layer toward the surface layer. 2. The process as set forth in claim 1 wherein the dislocations are glided to the substrate-surface layer interface and form misfit interfacial dislocations at the interface. 3. The process as set forth in claim 1 wherein the substrate is composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenic, indium gallium arsenic or any combination thereof. 4. The process as set forth in claim 1 wherein the surface layer is composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide or any combination thereof. 5. The process as set forth in claim 1 wherein the surface layer is composed of silicon germanium and the substrate is composed of silicon. 6. The process as set forth in claim 1 wherein the substrate is composed of silicon. 7. The process as set forth in claim 1 wherein the dislocation source layer is formed by any one of: slicing the substrate from an ingot comprising semiconductor material;lapping the back surface of the substrate;sand blasting the back surface of the substrate; orimplanting ions into the substrate through the back surface of the substrate. 8. The process as set forth in claim 1 wherein the substrate is heated to at least about 550° C. while radially distending the heterostructure. 9. The process as set forth in claim 1 wherein a stress is applied to the heterostructure during the radial distension, the stress being at least about 5 MPa. 10. The process as set forth in claim 1 wherein the substrate is radially distended for a period of at least about 10 seconds. 11. The process as set forth in claim 1 wherein the step of radially distending the substrate comprises radially distending the heterostructure. 12. The process as set forth in claim 1 wherein a stress S1 is applied to the heterostructure during the radial distension, the method further comprising reducing the stress S1 to a stress S2, S2 being less than S1, S2 being a stress less than a threshold value at which dislocations are generated from the dislocation source and above a threshold value which allows the existing dislocations to glide toward the substrate-surface layer interface to produce a substrate substantially free of dislocations. 13. The process as set forth in claim 1 wherein the surface layer is substantially free of threading dislocations. 14. The process as set forth in claim 1 wherein the surface layer continuously extends across the diameter of the substrate. 15. The process as set forth in claim 1 wherein the surface layer comprises discontinuous segments. 16. A process for preparing a relaxed heterostructure, the process comprising: depositing a surface layer on a front surface of the semiconductor substrate thereby creating a strain between the surface layer and the substrate;relaxing the strain in the surface layer and the substrate by the process of claim 1. 17. The process as set forth in claim 16 wherein the semiconductor substrate has a lattice constant, aS, and the surface layer has a lattice constant, aSL, the ratio aSL/aS being greater than about 1. 18. The process as set forth in claim 1 wherein the surface layer has a concentration of threading dislocations of less than about 104 threading dislocations/cm2. 19. A method for radially distending a semiconductor structure, the structure having a front surface, a back surface and a circumferential edge, the method comprising: positioning the substrate into an apparatus, the apparatus including a structure holder comprising a top plate and a back plate, the back plate contacting the structure adjacent a circumferential edge of the structure, the top plate contacting the front surface of the structure and the back plate contacting the back surface of the structure;forming a peripheral chamber between the top plate, back plate and circumferential edge of the structure; anddecreasing the pressure in the peripheral chamber to radially distend the structure.
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