IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0213953
(2014-03-14)
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등록번호 |
US-9583701
(2017-02-28)
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발명자
/ 주소 |
- Gee, Harry Yue
- Maxwell, Steven Patrick
- Vasquez, Jr., Natividad
- Clark, Mark Harold
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출원인 / 주소 |
|
대리인 / 주소 |
Amin, Turocy & Watson, LLP
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인용정보 |
피인용 횟수 :
1 인용 특허 :
191 |
초록
▼
A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resist
A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.
대표청구항
▼
1. A two-terminal memory device, comprising: a first metal electrode above a first oxide layer over a semiconductor substrate;a pillar structure comprising: a contact material layer on a top surface of the first metal electrode, wherein the contact material layer is semiconductive; anda switching la
1. A two-terminal memory device, comprising: a first metal electrode above a first oxide layer over a semiconductor substrate;a pillar structure comprising: a contact material layer on a top surface of the first metal electrode, wherein the contact material layer is semiconductive; anda switching layer on top of the contact material layer, wherein the switching layer comprises a portion of the contact material layer that is ionized, and wherein the switching layer has a lower conductivity than a portion of the contact material layer that is not ionized; anda second metal electrode above and in contact with a top surface of the pillar, wherein the second metal electrode comprises: an active metal layer in contact with the top surface of the switching layer of the pillar; anda conductor layer in contact with the active material. 2. The two-terminal memory device of claim 1, wherein the contact material layer is selected from a group consisting of: doped polysilicon, doped SiGe, or doped siliconcontaining material. 3. The two-terminal memory device of claim 1, the switching layer is selected from a group consisting of: non-conductive amorphous silicon, intrinsic semiconductor material, non-stoichiometric silicon oxide. 4. The two-terminal memory device of claim 1, wherein the active metal layer is selected from a group consisting of: aluminum, copper, tungsten, titanium, silver, platinum, palladium, Ti, TiN, Ag, TiW, and W. 5. The two-terminal memory device of claim 1, wherein the contact material layer is ionized with ions selected from a group consisting of: H, O, Si, Ag, or Ar. 6. The two-terminal memory device of claim 1, wherein the pillar structure is surrounded by an oxide layer. 7. The two-terminal memory device of claim 6, wherein the active material layer comprises a collar of an active metal material above the top surface of the pillar structure. 8. The two-terminal memory device of claim 6, wherein a cross-section of the pillar structure is selected from a group consisting of: a quadrilateral, an ovoid, round, and polygonal. 9. The two-terminal memory device of claim 1, wherein the implanted ions amorphize a structure of the switching layer. 10. The two-terminal memory device of claim 1, wherein the implanted ions comprise an ion implant profile having an implant power of at least 5 keV. 11. The two-terminal memory device of claim 1, wherein the implanted ions have a density of at least 5×1014 atoms/cm3. 12. The two-terminal memory device of claim 1, wherein the first oxide layer comprises a blanket oxide layer above the bottom metal electrodes that is planarized to expose a top surface of the bottom metal electrodes. 13. The two-terminal memory device of claim 1, further comprising a second oxide layer comprising a blanket oxide layer above the pillar that is planarized to expose a top surface of the pillar. 14. An electronic device comprising an electronic memory unit, the electronic memory unit comprising one or more arrays of multi-state memory cells configured to store information, the multi-state memory cells comprising: a first metal electrode above a first oxide layer over a semiconductor substrate;a pillar structure comprising:a contact material layer formed of a semiconductive contact material on a top surface of the first metal electrode, and a switching layer on top of the contact material layer, wherein the switching layer comprises a portion of the conductive contact material layer that is ionized to decrease conductivity of the switching layer relative to a portion of the contact material layer that is not ionized; anda second metal electrode above and in contact with a top surface of the pillar, wherein the second metal electrode comprises:an active metal layer in contact with the top surface of the switching layer of the pillar, and a conductor layer in contact with the active metal layer. 15. The electronic device of claim 14, wherein the contact material is selected from a group consisting of: doped polysilicon, doped SiGe, or doped silicon-containing material. 16. The electronic device of claim 14, wherein the switching layer is ionized via ion implantation with an ion implant profile having an implant power of at least 5 keV and wherein the implanted ions have a density of at least 5×1014 atoms/cm3. 17. The electronic device of claim 14 wherein the active metal layer comprises a material selected from a group consisting of: aluminum, copper, tungsten, titanium, silver, platinum, palladium, Ti, TiN, Ag, TiW, and W. 18. The electronic device of claim 14wherein the conductor layer comprises a barrier material layer on top of the active metal layer and a conductive material layer on top of the barrier material layer;wherein the barrier material layer is selected from a group consisting of: a tungsten material, a titanium material, and a metal nitride; andwherein the conductive material layer is selected from a group consisting of: aluminum and copper. 19. The electronic device of claim 14 wherein the portion of the conductive contact material layer that is ionized to decrease conductivity is selected from a group consisting of: undoped amorphous silicon, non-stoichiometric silicon oxide, and SiOx. 20. The electronic device of claim 14 wherein the portion of the conductive contact material that is ionized to decrease conductivity contacts the active metal layer.
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