초록 ▼

An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using

An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

대표청구항 ▼

1. An image sensor comprising: a pixel array including,a plurality of pixels including at least a first pixel and a second pixel,first and second row selection lines separated from each other, andfirst and second column lines separated from each other; anda column selecting circuit configured to con

1. An image sensor comprising: a pixel array including,a plurality of pixels including at least a first pixel and a second pixel,first and second row selection lines separated from each other, andfirst and second column lines separated from each other; anda column selecting circuit configured to connect the first column line to the second column line using a column selection signal,the first pixel being connected to the first row selection line and the first column line, andthe second pixel being in the same row as the first pixel and connected to the second row selection line and the second column line. 2. The image sensor of claim 1, wherein the column selecting circuit is configured to output a signal to a sampling circuit, the sampling circuit including an analog-to-converter (ADC). 3. The image sensor of claim 1, wherein the first pixel includes, a first drive transistor configured to receive an output of a first photodiode and generate a source-drain current based on the output of the first photodiode, anda first select transistor connected to the first row selection line and configured to provide an output of the first drive transistor to the first column line, andthe second pixel includes, a second drive transistor configured to receive an output of a second photodiode and generate a source-drain current based on the output of the second photodiode, anda second select transistor connected to the second row selection line and configured to provide an output of the second drive transistor to the second column line. 4. The image sensor of claim 1, wherein the plurality of pixels are in a Bayer pattern. 5. The image sensor of claim 4, further comprising: a control circuit configured to supply at least one control signal to the first pixel and the second pixel such that the first pixel has a longer exposure time than an exposure time of the second pixel. 6. The image sensor of claim 5, wherein the plurality of pixels are in a chess mosaic pattern. 7. The image sensor of claim 4, wherein the pixel array further comprises: a third pixel connected to the first column line and the second row selection line, wherein the first and second pixels include sensing pixels, and the third pixel includes a phase-difference detection pixel. 8. The image sensor of claim 7, wherein the pixel array further includes third and fourth column lines separated from the first and second column lines,the column selection signal includes first and second column selection signal parts, andthe column selecting circuit is configured to connect the first and second column lines using the first column selection signal part and connect the third and fourth column lines using the second column selection signal part. 9. The image sensor of claim 1, further comprising: a third row selection line separated from the first and second row selection lines;a third column line separated from the first and second column lines; andthe plurality of pixels includes a third pixel, the third pixel being in the same row of the pixel array as the first pixel and connected to the third row selection line and the third column line. 10. The image sensor of claim 9, wherein each of the first, second and third pixels comprises a first subpixel and a second subpixel, and the first subpixel and the second subpixel share a select transistor. 11. A pixel array including, a plurality of pixels,first and second row selection lines separated from each other, and column lines intersecting the first and second row selection lines, the column lines including first and second column lines which are separated from each other;a row scanning circuit configured to control the first and second row selection lines;a column selecting circuit configured to connect the first column line to the second column line using a column selection signal and to connect the connected first and second column lines to a sampling circuit; andthe sampling circuit configured to receive outputs of the column lines and convert the received outputs into digital signals,the first and second row selection lines being in each row of the pixel array, and at least one select transistor in a number of the plurality of pixels is connected to one of the first and second row selection lines. 12. The image sensor of claim 11, wherein the column lines further includes third and fourth column lines which are separated from the first and second column lines,the column selection signal includes a first column selection signal part and a second column selection signal part, andthe column selecting circuit is configured to connect the first and second column lines based on the first column selection signal part and to connect the third and fourth column lines based on the second column selection signal part. 13. The image sensor of claim 12, wherein pixels connected to the first through third column lines are all connected to the first row selection line, and pixels connected to the fourth column line include a first pixel connected to the first row selection line and a second pixel connected to the second row selection line. 14. The image sensor of claim 13, wherein the first pixel includes a phase-difference detection pixel, and the second pixel includes a sensing pixel. 15. An image sensor comprising: a pixel array having rows and columns of pixels, the rows connected to first and second selection lines and the pixel array having first exposure pixels and second exposure pixels;a control circuit configured to supply at least one control signal to the pixels such that an exposure time of the first exposure pixels is greater than an exposure time of the second exposure pixels; anda column selecting circuit configured to connect a first number of columns of pixels to a second number of columns of pixels based on an operating mode of the image sensor. 16. The image sensor of claim 15, further comprising: a row scanning circuit configured to output selection signals to the first and second selection lines, respectively, the column selecting circuit configured to combine outputs of only the first exposure pixels based on the selection signals and to combine outputs of only the second exposure pixels based on the selection signals. 17. The image sensor of claim 15, wherein the operating mode is one of a binning mode and a non-binning mode. 18. The image sensor of claim 15, wherein two pixels in a same column are connected to a same selection line. 19. The image sensor of claim 15, wherein the pixel array further includes a third selection line, and a first pixel in a first row and a second pixel in the second row are connected to the third selection line.