Representative implementations of devices and techniques provide a linearized high-ohmic resistor. In an example, a quantity of serially connected nonlinear impedances is arranged as a resistance. In one example, the quantity of impedances is applied in an amplifier circuit, between an input of the
Representative implementations of devices and techniques provide a linearized high-ohmic resistor. In an example, a quantity of serially connected nonlinear impedances is arranged as a resistance. In one example, the quantity of impedances is applied in an amplifier circuit, between an input of the amplifier and an output of the amplifier, and arranged to set a DC operating point for the amplifier.
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1. A device, comprising: a plurality of serially connected nonlinear impedances coupled between at least two terminals;a voltage divider arranged to divide a voltage between the at least two terminals substantially equally, to bias the nonlinear impedances;a buffer coupled to a first end of the volt
1. A device, comprising: a plurality of serially connected nonlinear impedances coupled between at least two terminals;a voltage divider arranged to divide a voltage between the at least two terminals substantially equally, to bias the nonlinear impedances;a buffer coupled to a first end of the voltage divider and to one of the at least two terminals; andwherein the buffer comprises an amplifier portion and an output stage portion, the output stage portion having a transistor biased by a first current source and a reference resistor biased by a second current source. 2. The device of claim 1, wherein one or more of the nonlinear impedances of the plurality of serially connected nonlinear impedances comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) device. 3. The device of claim 2, wherein a gate terminal of the MOSFET device is biased based on a voltage at a node of the voltage divider. 4. The device of claim 1, wherein each of the nonlinear impedances of the plurality of serially connected nonlinear impedances comprises a transistor device, and wherein a gate terminal of each transistor device is biased such that each transistor sees approximately a same gate overdrive. 5. The device of claim 1, wherein the plurality of serially connected nonlinear impedances provides a more linear impedance response than an impedance response of a single nonlinear impedance of the plurality of nonlinear impedances, for a same input signal. 6. The device of claim 1, the voltage divider further comprising a plurality of resistors. 7. The device of claim 1, wherein the voltage divider is arranged to divide the voltage between the at least two terminals to result in one or more predetermined voltage values. 8. The device of claim 1, wherein the buffer comprises a simple buffer or a level-shifting buffer. 9. The device of claim 1, wherein the buffer comprises an electrical circuit having one or more transistors. 10. The device of claim 1, wherein the output stage portion is arranged to provide a bias to at least one of the plurality of nonlinear impedances, the bias comprising a buffered version of an input signal increased or reduced by a diode voltage drop reduced or increased by a voltage drop over the reference resistor. 11. A circuit, comprising: an inverting amplifier;a signal source capacitively coupled to a first input of the inverting amplifier;a plurality of serially connected transistor devices coupled between the first input of the inverting amplifier and an output of the inverting amplifier, the plurality of transistor devices arranged to set a direct-current (DC) operating point for the inverting amplifier; andone or more buffer devices arranged to replicate a signal at the first input of the inverting amplifier. 12. The circuit of claim 11, further comprising a capacitance coupled in parallel with the plurality of transistor devices. 13. The circuit of claim 11, further comprising a plurality of voltage dividing resistors arranged to generate gate signals for the plurality of transistor devices. 14. The circuit of claim 11, the first input of the inverting amplifier further including a metal-oxide-semiconductor field-effect transistor (MOSFET) device gate. 15. The circuit of claim 11, wherein the plurality of transistor devices is arranged to operate as a substantially linear impedance. 16. A method, comprising: electrically coupling a plurality of transistor devices in series;providing a predetermined bias to gates of the plurality of transistor devices such that a bias value at a gate of a transistor device of the plurality of transistor devices substantially follows a signal the transistor device passes through a channel of the transistor device; andusing the plurality of transistor devices as a resistive component in at least a portion of a circuit. 17. The method of claim 16, further comprising biasing the gates of the plurality of transistors such that each of the transistors sees approximately a same gate overdrive. 18. The method of claim 16, wherein the bias value comprises the signal with a predetermined offset. 19. The method of claim 16, further comprising generating a replica of the signal using one or more buffers and a voltage divider, adding an offset to the replica, and providing the offset replica to the gates. 20. The method of claim 16, further comprising assigning a predetermined resistance value to the plurality of serially connected transistor devices. 21. The method of claim 20, wherein the predetermined resistance value is determined based on a diode voltage drop reduced or increased by a voltage drop over a reference impedance. 22. The device of claim 1, wherein the buffer is further coupled to a gate of one of the nonlinear impedances. 23. The device of claim 1, wherein the buffer is a single input single output buffer.
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