A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overly
A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.
대표청구항▼
1. A semiconductor device comprising: a gate stack overlying a substrate;a spacer on sidewalls of the gate stack, wherein a top surface of the spacer is above a top surface of the gate stack;a continuous protection layer overlying the gate stack and completely filling a space surrounded by the space
1. A semiconductor device comprising: a gate stack overlying a substrate;a spacer on sidewalls of the gate stack, wherein a top surface of the spacer is above a top surface of the gate stack;a continuous protection layer overlying the gate stack and completely filling a space surrounded by the spacer above the top surface of the gate stack, wherein the continuous protection layer is in direct contact with the substrate; anda contact hole over the spacer, wherein the contact hole extends over the gate stack, and wherein a sidewall of the contact hole has a step-wise shape,wherein an outer surface of the spacer forms an interface with the contact hole. 2. The semiconductor device according to claim 1, wherein a distance between the top surface of the spacer and the top surface of the gate stack is at least 200 Angstroms (Å). 3. The semiconductor device according to claim 1, wherein the continuous protection layer comprises at least one selected from silicon nitride, silicon oxynitride, or silicon oxide. 4. The semiconductor device according to claim 1, further comprising a dielectric layer overlying the continuous protection layer. 5. The semiconductor device according to claim 1, further comprising a liner layer between the gate stack and the spacer. 6. The semiconductor device according to claim 5, wherein the liner layer has a thickness ranging from 15 Å to 100 Å. 7. A semiconductor device, comprising: a gate stack overlying an active area, wherein the active area comprises a source region and a drain region;a spacer on sidewalls of the gate stack;a conductive material extending upward from at least one of the source region or the drain region;an elevated contact structure over the at least one of the source region or the drain region, wherein the elevated contact structure extends over at least a portion of the spacer; anda protection layer over the gate stack and the conductive material, wherein the protection layer exposes a portion of the conductive material, the protective layer extends along the gate stack and separates the elevated contact structure from the gate stack, and a thickness of the protection layer over the source region or the drain region is less than a thickness of the protection layer over the gate stack. 8. The semiconductor device according to claim 7, wherein the elevated contact structure comprises cobalt tungsten phosphide. 9. The semiconductor device according to claim 7, wherein the elevated contact structure has a thickness ranging from 20 nanometers (nm) to 50 nm. 10. The semiconductor device according to claim 7, wherein the conductive material comprises at least one of aluminum, copper, or tungsten. 11. The semiconductor device according to claim 7, wherein the gate stack comprising a gate dielectric between a gate electrode and the active area. 12. The semiconductor device according to claim 11, wherein the gate electrode comprises Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, or MoN. 13. The semiconductor device according to claim 7, wherein the spacer comprises silicon nitride, silicon carbide, or silicon oxynitride. 14. The semiconductor device according to claim 7, wherein at least one of the source region or the drain region comprises a silicided region. 15. A semiconductor device, comprising: a gate stack overlying a substrate;a spacer on sidewalls of the gate stack, wherein a top surface of the spacer is above a top surface of the gate stack;a continuous protection layer overlying the gate stack and filling an entirety of a space surrounded by the spacer above the top surface of the gate stack, wherein the continuous protection layer is in direct contact with the substrate; anda contact hole over the spacer,wherein an outer surface of the spacer forms an interface with the contact hole. 16. The semiconductor device according to claim 15, wherein the substrate comprises lightly doped source and drain regions. 17. The semiconductor device according to claim 16, wherein at least one of the lightly doped source region or the lightly doped drain region comprises a silicided region. 18. The semiconductor device according to claim 15, wherein the spacer comprises silicon nitride, silicon carbide, or silicon oxynitride. 19. The semiconductor device according to claim 15, wherein the gate stack comprising a gate dielectric between a gate electrode and the substrate. 20. The semiconductor device according to claim 19, wherein the gate electrode comprises Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, or MoN.
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이 특허에 인용된 특허 (19)
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