VLIW processor, instruction structure, and instruction execution method
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/00
G06F-009/44
G06F-009/30
G06F-009/38
출원번호
US-0989647
(2016-01-06)
등록번호
US-9606798
(2017-03-28)
우선권정보
JP-2011-262706 (2011-11-30)
발명자
/ 주소
Kobayashi, Yuki
출원인 / 주소
Renesas Electronics Corporation
대리인 / 주소
McGinn IP Law Group, PLLC
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
A processor, includes a first comparison operation unit; a second comparison operation unit; a first operation unit; a second operation unit; a third operation unit; and a register, wherein the first comparison operation unit receives a first comparison operation signal, a first input signal, and a
A processor, includes a first comparison operation unit; a second comparison operation unit; a first operation unit; a second operation unit; a third operation unit; and a register, wherein the first comparison operation unit receives a first comparison operation signal, a first input signal, and a second input signal, performs a comparison operation indicated by the first comparison operation signal on the first input signal and the second input signal, and outputs a result of the comparison operation, the second comparison operation unit receives a second comparison operation signal, a third input signal, and a fourth input signal, performs a comparison operation indicated by the second comparison operation signal on the third input signal and the fourth input signal, and outputs a result of the comparison operation, the first operation unit receives the comparison result of the first comparison operation unit.
대표청구항▼
1. A processor, comprising: a first comparison operation unit;a second comparison operation unit;a first operation unit;a second operation unit;a third operation unit; anda register, whereinthe first comparison operation unit receives a first comparison operation signal, a first input signal, and a
1. A processor, comprising: a first comparison operation unit;a second comparison operation unit;a first operation unit;a second operation unit;a third operation unit; anda register, whereinthe first comparison operation unit receives a first comparison operation signal, a first input signal, and a second input signal, performs a comparison operation indicated by the first comparison operation signal on the first input signal and the second input signal, and outputs a result of the comparison operation,the second comparison operation unit receives a second comparison operation signal, a third input signal, and a fourth input signal, performs a comparison operation indicated by the second comparison operation signal on the third input signal and the fourth input signal, and outputs a result of the comparison operation,the first operation unit receives the comparison result of the first comparison operation unit, and a value already held in the register, and outputs, as a first operation result, one of the comparison result of the first comparison operation unit, a first logical operation of the comparison result of the first comparison operation unit and the value of the register, and a second logical operation of the comparison result of the first comparison operation unit and the value of the register,the second operation unit receives the comparison result of the second comparison operation unit, and a value already held in the register, and outputs, as a second operation result, one of the comparison result of the second comparison operation unit, a first logical operation of the comparison result of the second comparison operation unit and the value of the register, and a second logical operation of the comparison result of the second comparison operation unit and the value of the register,the third operation unit receives the first operation result and the second operation result, and outputs, as an execution result, one of the first operation result, a first logical operation of the first operation result and the second operation result, and a second logical operation of the first operation result and the second operation result to the register, andthe register newly holds and outputs the execution result received from the third operation unit. 2. The processor according to claim 1, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation, further comprising a control unit that executes one instruction including a first compare instruction, a first synthesis designation, a second compare instruction, a second synthesis designation, and a third synthesis designation, the first synthesis designation corresponding to the first compare instruction and indicating one of “not to synthesize”, “AND”, and “OR”, the second synthesis designation corresponding to the second compare instruction and indicating one of “not to synthesize”, “AND”, and “OR”, the third synthesis designation indicating one of “AND” and “OR”. 3. The processor according to claim 2, wherein the control unit outputs signals as the first comparison operation signal, the first input signal, and the second input signal, respectively, to the first comparison operation unit, the signals respectively indicating a comparison operator and two input operands included in the first compare instruction, andthe control unit outputs signals as the second comparison operation signal, the third input signal, and the fourth input signal, respectively, to the second comparison operation unit, the signals respectively indicating a comparison operator and two input operands included in the second compare instruction. 4. The processor according to claim 3, wherein, when the second compare instruction is empty or when the third synthesis designation is empty, the control unit outputs, to the first comparison operation unit, the first comparison operation signal corresponding to the first compare instruction, the first input signal, and the second input signal, and outputs, to the third operation unit, a signal indicating that the first operation result is output as the execution result. 5. The processor according to claim 1, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation, and wherein the first operation unit comprises: a first AND gate and a first OR gate, each of the first AND gate and the first OR gate being configured to receive the comparison result of the first comparison operation unit and a value already held in the register; anda first selector that receives the comparison result of the first comparison operation unit, an output of the first AND gate, and an output of the first OR gate, andthe first selector selects one of three inputs as the first operation result, and outputs the selected input. 6. The processor according to claim 1, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation, and wherein the second operation unit comprises: a second AND gate and a second OR gate, each of the second AND gate and the second OR gate being configured to receive the comparison result of the second comparison operation unit and a value already held in the register; anda second selector that receives the comparison result of the second comparison operation unit, an output of the second AND gate, and an output of the second OR gate, andthe second selector selects one of three inputs as the second operation result, and outputs the selected input. 7. The processor according to claim 1, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation, and wherein the third operation unit comprises: a third AND gate and a third OR gate, each of the third AND gate and the third OR gate being configured to receive the first operation result and the second operation result; anda third selector that receives the first operation result, an output of the third AND gate, and an output of the third OR gate, andthe third selector selects one of three inputs as the execution result, and outputs the selected input. 8. The processor according to claim 1, wherein the register comprises a predicate register. 9. The processor according to claim 1, wherein the first logical operation comprises an AND operation. 10. The processor according to claim 1, wherein the second logical operation comprises an OR operation. 11. An instruction structure of an instruction, comprising: a first compare instruction field that stores a first compare instruction;a first synthesis designation field that stores a first synthesis designation;a second compare instruction field that stores a second compare instruction;a second synthesis designation field that stores a second synthesis designation; anda third synthesis designation field that stores a third synthesis designation,the first synthesis designation indicates, as a first operation result, one of a result of a comparison indicated by the first compare instruction, a first logical operation of the result of the comparison and an execution result of a preceding instruction, and a second logical operation of the result of the comparison and the execution result of the preceding instruction,the second synthesis designation indicates, as a second operation result, one of a result of a comparison indicated by the second compare instruction, a first logical operation of the result of the comparison and the execution result of the preceding instruction, and a second logical operation of the result of the comparison and the execution result of the preceding instruction, andthe third synthesis designation indicates, as an execution result of a current instruction, one of the first operation result, a first logical operation of the first operation result and the second operation result, and a second logical operation of the first operation result and the second operation result. 12. The instruction structure according to claim 11, wherein, when one of the second compare instruction field and the third synthesis designation field is empty, the empty field indicates that the first operation result is output as the execution result of the current instruction. 13. The instruction structure according to claim 11, wherein the first logical operation comprises an AND operation. 14. The instruction structure according to claim 11, wherein the second logical operation comprises an OR operation. 15. The instruction structure according to claim 11, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation. 16. A method for executing an instruction in a processor, the processor comprising a register and configured to receive an instruction including a first compare instruction, a second compare instruction, and three synthesis designations including first and second synthesis designations each indicating one of “not to synthesize”, “a first logical operation”, and “a second logical operation”, and a third synthesis designation indicating one of “a first logical operation” and “a second logical operation”, the method comprising: outputting, as a first operation result, a result of a comparison indicated by the first compare instruction when the first synthesis designation indicates “not to synthesize”, and in other cases, outputting, as the first operation result, a value obtained by performing a logical operation indicated by the first synthesis designation on the result of the comparison indicated by the first compare instruction and a value already held in the register;outputting, as a second operation result, a result of a comparison indicated by the second compare instruction when the second synthesis designation indicates “not to synthesize”, and in other cases, outputting, as the second operation result, a value obtained by performing a logical operation indicated by the second synthesis designation on the result of the comparison indicated by the second compare instruction and a value already held in the register;outputting, as an execution result of a current instruction, a value obtained by performing a logical operation indicated by the third synthesis designation on the first operation result and the second operation result, to the register; andnewly holding and outputting, by the register, the execution result. 17. The execution method according to claim 16, wherein, when one of the second compare instruction and the third synthesis designation is empty, the first operation result is output to the register as the execution result of the current instruction. 18. The execution method according to claim 16, wherein the first logical operation comprises an AND operation. 19. The execution method according to claim 16, wherein the second logical operation comprises an OR operation. 20. The execution method according to claim 16, wherein the first logical operation comprises an AND operation, and the second logical operation comprises an OR operation.
Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
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