[특허]Pseudo-envelope following power management system

Pseudo-envelope following power management system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03G-003/00 H03F-001/02 H03F-003/189 H03F-003/24 H03F-003/19 H03F-003/21 H02M-003/07
출원번호	US-0638374 (2015-03-04)
등록번호	US-9621113 (2017-04-11)
발명자 / 주소	Khlat, Nadim Kay, Michael R.
출원인 / 주소	Qorvo US, Inc.
대리인 / 주소	Withrow + Terranova, P.L.L.C.
인용정보	피인용 횟수 : 0 인용 특허 : 205

초록

Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier.

대표청구항 ▼

1. A power management system for an RF power amplifier comprising: a parallel amplifier circuit comprising: an amplifier in communication with a power amplifier supply voltage; anda voltage offset loop circuit configured to provide a threshold offset current as a feedback signal; anda multi-level charge pump buck converter comprising: a switcher control circuit configured to receive the feedback signal from the voltage offset loop circuit and output a logic level indication; anda frequency lock loop (FLL) in communication with the switcher control circuit and receiving the logic level indication. 2. The power management system of claim 1, further comprising a coupling circuit coupled to an output of the parallel amplifier circuit, and wherein the feedback signal estimates a magnitude of an offset voltage appearing across the coupling circuit. 3. The power management system of claim 1, wherein the voltage offset loop circuit comprises a first subtractor circuit, the first subtractor circuit comprising a voltage offset output, the first subtractor circuit configured to receive the power amplifier supply voltage and an output from the parallel amplifier circuit. 4. The power management system of claim 3, wherein the voltage offset loop circuit comprises a second subtractor circuit, the second subtractor circuit comprising an input coupled to the voltage offset output and an offset error output. 5. The power management system of claim 4, wherein the voltage offset loop circuit comprises an integrator coupled to the offset error output and wherein the integrator comprises a threshold offset current output. 6. The power management system of claim 1 wherein as the threshold offset current rises above zero current, an output frequency of the multi-level charge pump buck converter is lowered. 7. The power management system of claim 6, further comprising a power inductor coupled to an output of the multi-level charge pump buck converter, wherein as the output frequency decreases, current output from the power inductor decreases. 8. The power management system of claim 7, wherein as the current output from the power inductor decreases, an offset voltage within the voltage offset loop circuit decreases. 9. The power management system of claim 1 wherein as the threshold offset current sinks below zero current, an output frequency of the multi-level charge pump buck converter is increased. 10. The power management system of claim 9, further comprising a power inductor coupled to an output of the multi-level charge pump buck converter, wherein as the output frequency increases, current output from the power inductor increases. 11. The power management system of claim 10, wherein as the current output from the power inductor increases, an offset voltage within the voltage offset loop circuit increases. 12. A method of controlling a power management system for an RF power amplifier, comprising: providing a threshold offset current as a feedback signal from a voltage offset loop circuit;receiving the feedback signal at a switcher control circuit of a multi-level charge pump buck converter;outputting a logic level indication from the switcher control circuit;receiving the logic level indication at a frequency lock loop (FLL). 13. The method of claim 12 further comprising estimating, with the feedback signal, a magnitude of an offset voltage appearing across a coupling circuit. 14. The method of claim 12, further comprising generating a threshold offset current output with an integrator in the voltage offset loop circuit. 15. The method of claim 12, further comprising lowering an output frequency of the multi-level charge pump buck converter as the threshold offset current rises above zero current. 16. The method of claim 12, further comprising increasing an output frequency of the multi-level charge pump buck converter as the threshold offset current sinks below zero current.

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Yanagida,Osamu; Komiya,Kunihiro, Step-up power supply unit and portable apparatus utilizing the same.
상세보기
Chae, Youngcheol; Han, Gunhee; Ham, Seog-Heon, Switched capacitor circuit with inverting amplifier and offset unit.
상세보기
Oraw, Bradley S.; Kumar, Pavan, Switched capacitor converters.
상세보기
Shah, Peter J; Mehdizad Taleie, Shahin; Groenewold, Gerrit; Miao, Guoqing; Sung, Eunyung, Switched-capacitor DC blocking amplifier.
상세보기
Witchard, Clyde, Switching amplifier.
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Arknaes-Pedersen, Lars, Switching amplifier driven by a controlled power supply.
상세보기
Melanson, John L., Switching power converter with efficient switching control signal period generation.
상세보기
Koren, Doron Shahar; Toujikov, Sergey, System and a method for amplifying a signal by multiple non-linear power amplifiers.
상세보기
Ralph Duncan ; Tom W. Kwan, System and method for narrow band PLL tuning.
상세보기
Sahota, Gurkanwal Singh, System and method for power control calibration and a wireless communication device.
상세보기
Conrad, Edward W.; Douglas, James C.; Goddard, Shawn R.; Smyth, John S., System and method of curve fitting.
상세보기
Lee, Chang-Ho; An, Kyu Hwan; Yang, Ki Seok; Chang, Jaejoon; Woo, Wangmyong; Kim, Younsuk; Kim, Haksun; Lee, Ockgoo; Lee, Dong Ho; Kim, Hyungwook; Laskar, Joy, Systems and methods for power amplifiers with voltage boosting multi-primary transformers.
상세보기
Xu, Bing; Tang, Clive; Rahman, Mahibur, Systems and methods for spurious emission cancellation.
상세보기
Lam Chung (Fremont CA), Test generator system for controllably inducing power pin latch-up and signal pin latch-up in a CMOS device.
상세보기
Hou, Zhaozheng; Liu, Xujun, Tracking power supply, method for controlling power supply, and communication apparatus.
상세보기
Wilson, Martin Paul, Transformer based voltage supply.
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Kumagai, Kazuhiko, Transmission device, distortion compensation device, and distortion compensation method.
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McCallister, Ronald Duane, Transmitter and method for RF power amplifier having a bandwidth controlled, detroughed envelope tracking signal.
상세보기
Christopher Todd J. (Indianapolis IN) Horlander Karl F. (Indianapolis IN) Saeger Timothy W. (Indianapolis IN), Two stage interpolation system.
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Rieger Martin (Rottweil DEX) Roth Sabine (Villingen-Schwenningen DEX), Universal active filter.
상세보기
Yoshikawa Kiyoshi,JPX, Variable delay circuit.
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McMorrow, Robert J.; Blanchard, Roxann, Variable filter systems and methods for enhanced data rate communication systems.
상세보기
Robinson,Ian; Winter,Frank, Variable supply amplifier system.
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Amerom, Jan; Jansen, Guus; Lopata, Douglas D.; Slomp, Marcel; Visee, Maarten, Versatile and intelligent power controller.
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Groom, Terry J.; Pullen, Stuart, Virtual ripple generation in switch-mode power supplies.
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Tamagawa Akio (Tokyo JPX), Voltage converting circuit and multiphase clock generating circuit used for driving the same.
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Hsieh, Chung An; Li, Cheng Tao, Voltage generating apparatus and methods.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Pseudo-envelope following power management system 원문보기

초록

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (205)

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연합인증

Pseudo-envelope following power management system 원문보기

초록

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (205)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

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