IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0566141
(2012-08-03)
|
등록번호 |
US-9632777
(2017-04-25)
|
발명자
/ 주소 |
- Fleischer, Bruce M.
- Fox, Thomas W.
- Jacobson, Hans M.
- Moreno, Jaime H.
- Nair, Ravi
- Prener, Daniel A.
|
출원인 / 주소 |
- INTERNATIONAL BUSINESS MACHINES CORPORATION
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
43 |
초록
▼
Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The pr
Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
대표청구항
▼
1. A method for packed loading and storing of data distributed in a system that includes memory and a processing element, the processing element comprising a vector computation register file comprising a plurality of register file entries, each of the register file entries comprising a plurality of
1. A method for packed loading and storing of data distributed in a system that includes memory and a processing element, the processing element comprising a vector computation register file comprising a plurality of register file entries, each of the register file entries comprising a plurality of register file elements, and the processing element further comprising a scalar computation register file comprising a same number of register file entries as the vector computation register file, each register file entry of the scalar computation register file with one register file element, the method comprising: fetching and decoding an instruction for execution by the processing element, wherein the instruction comprises at least one sub-instruction accessing the vector computation register file and at least one sub-instruction accessing the scalar computation register file in parallel;distributing in each of at least two separate register file elements of a first register file entry of the register file entries of the vector computation register file, an address of one of a first plurality of non-contiguous locations in the memory of a plurality of data elements to gather;gathering, by the processing element based on the instruction and addresses, the data elements from the first plurality of non-contiguous locations in the memory, wherein each of the data elements is individually addressable and is narrower than a width of the register file elements of the vector computation register file in the processing element; andpacking and loading the data elements into one or more of the register file elements of a second register file entry of the register file entries of the vector computation register file by the processing element based on the instruction, such that at least two of the data elements gathered from the first plurality of non-contiguous locations in the memory are packed and loaded into a single register file element of the second register file entry as a plurality of packed data elements in parallel with performing the at least one sub-instruction accessing the register file entries of the scalar computation register file. 2. The method of claim 1, wherein each of the addresses comprises a greater width than a width of each of the data elements. 3. The method of claim 2, wherein packing and loading the data elements into the one or more of the register file elements further comprises distributing the packed data elements into fewer register file elements than are consumed by the addresses, and the second register file entry is subsequent to the first register file entry in the vector computation register file. 4. The method of claim 1, further comprising: packing at least a first number of the data elements to fill the width of the register file elements of the vector computation register file; andpacking a second number of the data elements into less than the width of the register file elements of the vector computation register file. 5. The method of claim 1, further comprising: fetching and decoding a second instruction for execution by the processing element;unpacking the data elements from the second register file entry by the processing element based on the second instruction; andscattering and storing, by the processing element, the data elements to a second plurality of non-contiguous locations in the memory based on the second instruction. 6. The method of claim 5, wherein a plurality of addresses of the second plurality of non-contiguous locations in the memory of the data elements to scatter are distributed in separate register file elements of the vector computation register file. 7. The method of claim 6, wherein the addresses of the second plurality of non-contiguous locations in the memory of the data elements to scatter are different addresses than the addresses of the first plurality of non-contiguous locations in the memory from which the data elements are gathered. 8. The method of claim 6, wherein unpacking the data elements from the second register file entry by the processing element based on the second instruction further comprises reading the packed data elements as narrower data types and reading the plurality of addresses of the second plurality of non-contiguous locations in the memory as wider data types as compared to the narrower data types. 9. The method of claim 6, further comprising: unpacking at least a first number of the data elements filling the width of the register file elements; andunpacking a second number of the data elements occupying less than the width of the register file elements. 10. A method for packed loading and storing of data distributed in an active memory device that includes memory and a processing element, the processing element comprising a vector computation register file comprising a plurality of register file entries, each of the register file entries comprising a plurality of register file elements, and the processing element further comprising a scalar computation register file comprising a same number of register file entries as the vector computation register file, each register file entry of the scalar computation register file with one register file element, the method comprising: fetching and decoding an instruction from an instruction buffer in the processing element for execution by the processing element, wherein the instruction comprises at least one sub-instruction accessing the vector computation register file and at least one sub-instruction accessing the scalar computation register file in parallel;unpacking a plurality of data elements loaded in one or more of the register file elements of a second register file entry of the register file entries of the vector computation register file based on the instruction, wherein at least two of the plurality of data elements are unpacked from a single register file element of the second register file entry; andscattering and storing, by the processing element, the plurality of data elements to a plurality of non-contiguous locations in the memory based on the instruction and a plurality of addresses in parallel with performing the at least one sub-instruction accessing the register file entries of the scalar computation register file, wherein each of the plurality of data elements is individually addressable and is narrower than a width of the plurality of register file elements of the vector computation register file, wherein an address of one of the non-contiguous locations in the memory of each of the data elements to scatter is distributed in each of at least two separate register file elements of a first register file entry of the register file entries of the vector computation register file. 11. The method of claim 10, wherein the active memory device is a three-dimensional memory cube, the memory is divided into three-dimensional blocked regions as memory vaults, and the non-contiguous locations in the memory are accessed through one or more memory controllers in the active memory device. 12. The method of claim 10, wherein the unpacking of the plurality of data elements is performed by a load-store unit in parallel with instruction processing by an arithmetic-logic unit. 13. The method of claim 12, wherein the vector computation register file is accessible by the load-store unit and the arithmetic-logic unit, wherein each of the plurality of addresses comprises a greater width than a width of each of the plurality of data elements. 14. The method of claim 13, wherein unpacking the plurality of data elements from the one or more of the register file elements by the processing element further comprises reading packed data elements as narrower data types and reading the plurality of addresses as wider data types as compared to the narrower data types. 15. The method of claim 13, further comprising: fetching and decoding a second instruction from the instruction buffer of the processing element for execution by the processing element;gathering, by the processing element, a set of data elements from a set of non-contiguous locations in the memory based on the second instruction; andpacking and loading the set of data elements into a set of register file elements of a third register file entry of the vector computation register file by the processing element based on the second instruction. 16. The method of claim 15, wherein packing and loading the set of data elements into the set of register file elements by the processing element based on the second instruction further comprises distributing the set of packed data elements into fewer register file elements than are consumed by a plurality of addresses of the set of the non-contiguous locations in the memory to gather. 17. The method of claim 16, wherein the plurality of addresses of the non-contiguous locations in the memory of the data elements to scatter are different addresses than the plurality of addresses of the set of non-contiguous locations in the memory from which the set of data elements are gathered. 18. The method of claim 15, further comprising: packing at least a first number of the set of data elements to fill a width of the set of register file elements; andpacking a second number of the set of data elements into less than the width of the set of register file elements.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.