The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define
The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.
대표청구항▼
1. An intelligence cache, comprising: a general interface, a software define and reconfiguration unit, a control unit, a memory unit and an intelligence processing unit, wherein the general interface is configured to receive configuration information and/or control information, and/or data informati
1. An intelligence cache, comprising: a general interface, a software define and reconfiguration unit, a control unit, a memory unit and an intelligence processing unit, wherein the general interface is configured to receive configuration information and/or control information, and/or data information from a core or a bus, and return target data;the software define and reconfiguration unit is configured to define a memory as a required cache memory according to the configuration information;the control unit is configured to control writing and reading of the cache memory and monitor instructions and data streams in real time, and control the memory unit to load the required data in advance according to system information, features of tasks to be executed and features of data structures used;the memory unit is composed of a number of memory modules and configured to cache data; and the required cache memory is formed by the memory modules according to the definition of the software define and reconfiguration unit; andthe intelligence processing unit is configured to process input and output data, and transfer, convert and operate on data among multiple structures defined in the control unit;wherein the software define and reconfiguration unit is further configured to dynamically reconstruct idle memory modules in its operating process. 2. The intelligence cache according to claim 1, wherein the required cache memory can be configured as at least one of the following: Tightly Coupled Memory (TCM), Content Addressable Memory (CAM) and Cache. 3. The intelligence cache according to claim 1, wherein the general interface further comprises a coherent interface in a multi-core environment. 4. The intelligence cache according to claim 1, wherein the software define and reconfiguration unit is further configured to define cache memories with different properties and same structure, wherein the cache memories with different properties and same structure include at least one of the following: full associative cache, 16-way associative cache, 4-way associative cache, 2-way associative cache and direct-mapped cache. 5. The intelligence cache according to claim 1, wherein the intelligence processing unit transferring, converting and operating on data among multiple structures defined in the control unit comprises: matrix operation, bit level operation, data search, data sorting, data comparison, logic operation, setting/resetting, read-modify-write operations, and operations of increment, decrement, addition and subtraction. 6. The intelligence cache according to claim 1, wherein the intelligence processing unit is further configured to fill and update data and transfer data to a next-level memory. 7. The intelligence cache according to claim 1, wherein the control unit loads data according to the size of data blocks defined by the software define and reconfiguration unit or loads data automatically; and a dedicated memory area is defined in the memory unit to load abnormal or disordered control programs. 8. An intelligence terminal comprising the intelligence cache according to claim 1. 9. The intelligence terminal according to claim 8, comprising: a computer, a notebook, a cell phone, a personal digital assistant or a game machine. 10. The intelligence terminal according to claim 8, wherein the required cache memory can be configured as at least one of the following: Tightly Coupled Memory (TCM), Content Addressable Memory (CAM) and Cache. 11. The intelligence terminal according to claim 10, comprising: a computer, a notebook, a cell phone, a personal digital assistant or a game machine. 12. The intelligence terminal according to claim 8, wherein the general interface further comprises a coherent interface in a multi-core environment. 13. The intelligence terminal according to claim 12, comprising: a computer, a notebook, a cell phone, a personal digital assistant or a game machine. 14. The intelligence terminal according to claim 8, wherein the software define and reconfiguration unit is further configured to define cache memories with different properties and same structure, wherein the cache memories with different properties and same structure include at least one of the following: full associative cache, 16-way associative cache, 4-way associative cache, 2-way associative cache and direct-mapped cache. 15. The intelligence terminal according to claim 14, comprising: a computer, a notebook, a cell phone, a personal digital assistant or a game machine. 16. The intelligence terminal according to claim 8, wherein the software define and reconfiguration unit is further configured to dynamically reconstruct idle memory modules in the operating process. 17. The intelligence terminal according to claim 8, wherein the intelligence processing unit transferring, converting and operating on data among multiple structures defined in the control unit comprises: matrix operation, bit level operation, data search, data sorting, data comparison, logic operation, setting/resetting, read-modify-write operations, and operations of increment, decrement, addition and subtraction. 18. The intelligence terminal according to claim 8, wherein the intelligence processing unit is further configured to fill and update data and transfer data to a next-level memory. 19. The intelligence terminal according to claim 8, wherein the control unit loads data according to the size of data blocks defined by the software define and reconfiguration unit or loads data automatically; and a dedicated memory area is defined in the memory unit to load abnormal or disordered control programs.
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이 특허에 인용된 특허 (4)
Bradley L. Taylor, Local memory unit system with global access for use on reconfigurable chips.
Baumgartner Yoanna ; Benavides Alvaro Eduardo ; Dean Mark Edward ; Hollaway ; Jr. John Thomas, Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system.
Coyle William E. (Cary NC) Nuechterlein David W. (Durham NC) O\Donnell Kim E. (Raleigh NC) Sartorius Thomas A. (Raleigh NC) Schultz Kenneth D. (Cary NC) Wolters Emmy M. (Raleigh NC), Reconfigurable multi-way associative cache memory.
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