In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizo
In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer of a first metal having a first conductivity is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element. A portion of the non-reacted first metal is selectively removed. That portion of the first metal which has reacted to form the alloy liner on the patterned dielectric sidewall remains after the removal process. A second metal layer is deposited on the liner layer with a second metal on the liner and filling the conductive line trenches with the second metal layer. The second metal has a second conductivity higher than the first conductivity. A device fabricated by the method is another aspect of the invention.
대표청구항▼
1. A method for fabricating an advanced metal conductor structure comprising: providing a conductive line pattern including a set of conductive line trenches in a dielectric layer, each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom a
1. A method for fabricating an advanced metal conductor structure comprising: providing a conductive line pattern including a set of conductive line trenches in a dielectric layer, each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom and a patterned feature dimension;performing a surface treatment of the dielectric layer, the surface treatment producing an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased;depositing a first metal layer with a first metal having a first conductivity on the element enriched surface layer;performing a first thermal anneal which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating an alloy liner which is an alloy of the first metal and selected element;removing nonreacted portions of the first metal layer; anddepositing a second metal layer on the alloy liner and filling the conductive line trenches with the second metal layer, wherein the second metal has a second conductivity higher than the first conductivity within the patterned feature dimension. 2. The method as recited in claim 1 wherein the first metal layer is comprised of aluminum and the selected element is nitrogen. 3. The method as recited in claim 2, wherein the surface treatment is a nitridation process which increases the concentration of nitrogen in the element enriched surface layer and the liner is comprised of an alloy selected from the group consisting of AlN and Al(N, Si), and Al(N, Si, Mn). 4. The method as recited in claim 1, wherein the first metal layer is comprised of a metal selected from the group consisting of Al, Co, Ru, Ir, Rh, W, Mn and Ni and the second metal layer is a metal selected from the group of Cu, Co, W, Ir, Rh, Ni and Ru. 5. The method as recited in claim 1, wherein the selected element is selected from the group consisting of N, Si, C, and O. 6. The method as recited in claim 1, further comprising removing excess first alloy liner and second metal layers on field areas of the dielectric layer using a planarization process. 7. The method as recited in claim 6, wherein the planarization process is a chemical mechanical polishing process. 8. The method as recited in claim 1, wherein the second metal layer is selected from the group of CuMn, CoMn, WMn, IrMn, RhMn, NiMn and RuMn and wherein the second thermal anneal drives manganese into the liner. 9. The method as recited in claim 1, further comprising depositing a barrier layer on the alloy liner layer before the second metal layer.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (8)
Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
Kang Sang-bom,KRX ; Park Chang-soo,KRX ; Chae Yun-sook,KRX ; Lee Sang-in,KRX, Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same.
Fair, James A.; Havemann, Robert H.; Sung, Jungwan; Taylor, Nerissa; Lee, Sang-Hyeob; Plano, Mary Anne, Selective refractory metal and nitride capping.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.