Apparatus and methods for high voltage variable capacitor arrays with body biasing resistors
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03H-007/06
H01G-007/00
H01L-027/08
H03H-007/01
H03H-001/02
H03H-011/04
H03H-011/28
H03H-005/12
H03H-001/00
출원번호
US-0705381
(2015-05-06)
등록번호
US-9673774
(2017-06-06)
발명자
/ 주소
Madan, Anuj
Gupta, Dev V.
Lai, Zhiguo
출원인 / 주소
TDK CORPORATION
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
3인용 특허 :
29
초록▼
Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable ca
Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.
대표청구항▼
1. An integrated circuit comprising: a variable capacitor array including at least three variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, wherein each of the at least three variable capacitor cells includes: two or more pairs of anti-
1. An integrated circuit comprising: a variable capacitor array including at least three variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, wherein each of the at least three variable capacitor cells includes: two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series; anda plurality of body biasing resistors configured to bias a plurality of bodies of the two or more pairs of anti-series MOS capacitors with a body bias voltage; anda bias voltage generation circuit configured to bias at least a first variable capacitor cell of the at least three variable capacitor cells to control a capacitance of the variable capacitor array,wherein the integrated circuit does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array. 2. The integrated circuit of claim 1, wherein the bias voltage generation circuit is further configured to generate the body bias voltage. 3. The integrated circuit of claim 1, wherein the plurality of body biasing resistors of each of the at least three variable capacitor cells comprises: a first body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the first MOS capacitor of each of the at least three variable capacitor cells;a second body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the second MOS capacitor of each of the at least three variable capacitor cells;a third body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the third MOS capacitor of each of the at least three variable capacitor cells; anda fourth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the fourth MOS capacitor of each of the at least three variable capacitor cells. 4. The integrated circuit of claim 3, wherein the two or more pairs of anti-series MOS capacitors further comprises a third pair of anti-series MOS capacitors comprising a fifth MOS capacitor and a sixth MOS capacitor electrically connected in anti-series, wherein the plurality of body biasing resistors further comprises: a fifth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the fifth MOS capacitor; anda sixth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the sixth MOS capacitor. 5. The integrated circuit of claim 1, wherein each of the plurality of body biasing resistors has a resistance in the range of 10 kΩ to 10,000 kΩ. 6. The integrated circuit of claim 1, wherein the bias voltage generation circuit is configured to bias the first variable capacitor cell with a first bias voltage, wherein the bias voltage generation circuit is configured to control the first bias voltage to a voltage level selected from a discrete number of two or more bias voltage levels. 7. The integrated circuit of claim 6, wherein the first MOS capacitor of each of the at least three variable capacitor cells and the second MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a first intermediate node of each of the at least three variable capacitor cells, wherein the third MOS capacitor of each of the at least three variable capacitor cells and the fourth MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a second intermediate node of each of the at least three variable capacitor cells, wherein the first variable capacitor cell further comprises: a first control biasing resistor electrically connected between the first intermediate node of the first variable capacitor cell and the first bias voltage; anda second control biasing resistor electrically connected between the second intermediate node of the first variable capacitor cell and the first bias voltage. 8. The integrated circuit of claim 1, wherein a gate of the first MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a gate of the third MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the fourth MOS capacitor of each of the at least three variable capacitor cells. 9. The integrated circuit of claim 1, wherein a source and a drain of the first MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a source and a drain of the third MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the fourth MOS capacitor of each of the at least three variable capacitor cells. 10. An apparatus comprising: a radio frequency (RF) input;an RF output;at least three variable capacitor cells electrically connected in parallel between the RF input and the RF output, wherein each of the at least three variable capacitor cells includes: two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series; anda plurality of body biasing resistors configured to bias a plurality of bodies of the two or more pairs of anti-series MOS capacitors with a body bias voltage; anda bias voltage generation circuit configured to generate a first bias voltage, wherein the bias voltage generation circuit is configured to bias the two or more pairs of anti-series MOS capacitors of at least one of the three variable capacitor cells with the first bias voltage to control a capacitance of the at least one of the three variable capacitor cells,wherein each of the at least three variable capacitor cells does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array. 11. The integrated circuit of claim 1, wherein the integrated circuit is fabricated using a silicon on insulator (SOI) substrate. 12. The integrated circuit of claim 1, wherein each of the at least three variable capacitor cells comprises at least three pairs of anti-series MOS capacitors electrically connected in series between the RF input and the RF output. 13. The integrated circuit of claim 1, wherein the first MOS capacitor of each of the at least three variable capacitor cells and the second MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a first intermediate node of each of the at least three variable capacitor cells, wherein the first variable capacitor cell further comprises a first feed-forward capacitor electrically connected between the RF input and the first intermediate node of the first variable capacitor cell to provide a feed-forward path from the RF input to the first intermediate node of the first variable capacitor cell. 14. The integrated circuit of claim 13, wherein the third MOS capacitor of each of the at least three variable capacitor cells and the fourth MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a second intermediate node of each of the at least three variable capacitor cells wherein the first variable capacitor cell further comprises a second feed-forward capacitor electrically connected between the first intermediate node of the first variable capacitor cell and the second intermediate node of the first variable capacitor cell. 15. The integrated circuit of claim 14, wherein the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells further comprises a third pair of anti-series MOS capacitors comprising a fifth MOS capacitor of each of the at least three variable capacitor cells and a sixth MOS capacitor of each of the at least three variable capacitor cells electrically connected in anti-series and electrically connected to one another at a third intermediate node of each of the at least three variable capacitor cells, wherein the first variable capacitor cell further comprises a third feed-forward capacitor electrically connected between the second intermediate node of the first variable capacitor cell and the third intermediate node of the first variable capacitor cell. 16. The integrated circuit of claim 15, wherein the first feed-forward capacitor has a capacitance value that is greater than that of the second feed-forward capacitor, and wherein the second feed-forward capacitor has a capacitance value that is greater than that of the third feed-forward capacitor. 17. A method of providing a variable capacitance in a radio frequency (RF) system, the method comprising: generating a plurality of bias voltages including a first bias voltage using a bias voltage generation circuit;controlling a voltage level of the first bias voltage based on a control signal using the bias voltage generation circuit;biasing a first variable capacitor cell of at least three variable capacitor cells connected in parallel of a variable capacitor array using the first bias voltage, wherein each of the at least three variable capacitor cells includes two or more pairs of anti-series MOS capacitors electrically connected in series between a radio frequency (RF) input and an RF output of the variable capacitor array, the variable capacitor array does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array; andbiasing a plurality of bodies of the two or more pairs of anti-series MOS capacitors of at least a first variable capacitor cell with a body bias voltage using a plurality of body biasing resistors. 18. The method of claim 17, further comprising generating the body bias voltage using the bias voltage generation circuit. 19. The method of claim 17, wherein a first pair of the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series and electrically connected to one another at a first node of each of the at least three variable capacitor cells, wherein the method further comprises providing a first feed-forward path from the RF input to the first intermediate node using a first feed-forward capacitor.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (29)
Gallichio Michael J. (New Milford CT), Anti-parallel capacitor.
Alacoque, Jean-Claude, Galvanic isolation device for direct current electrical signals or electrical signals likely to include a direct current component.
Mucke Lars Henrik ; Hull Christopher Dennis ; Jansson Lars Gustaf, Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors.
Carns, Timothy K.; Horvath, John L.; DeBruler, Lee J.; Westphal, Michael J., Method of fabricating high-performance capacitors in integrated MOS technologies.
Emesh Ismail T. (Cumberland CAX) Calder Iain D. (Kanata CAX) Ho Vu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Madsen Lynnette D. (Ottawa CAX), Structure and method of making a capacitor for an intergrated circuit.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.