최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0181556 (2014-02-14) |
등록번호 | US-9673825 (2017-06-06) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 551 |
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate i
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.
1. An exclusive-nor logic circuit, comprising: a first input node;a second input node;an output node;a pass gate connected to be controlled by a logic state present at the second input node, the pass gate connected to pass through a version of a logic state present at the first input node to the out
1. An exclusive-nor logic circuit, comprising: a first input node;a second input node;an output node;a pass gate connected to be controlled by a logic state present at the second input node, the pass gate connected to pass through a version of a logic state present at the first input node to the output node when controlled to transmit by the logic state present at the second input node;a transmission gate connected to be controlled by the logic state present at the first input node, the transmission gate connected to pass through a version of the logic state present at the second input node to the output node when controlled to transmit by the logic state present at the first input node;pulldown logic connected to be controlled by both the logic state present at the first input node and the logic state present at the second input node, the pulldown logic connected to drive a state present at the output node high when both the logic state present at the first input node and the logic state present at the second input node are low;a first input inverter having an input connected to the first input node and an output connected to the pass gate;a second input inverter having an input connected to the second input node and an output connected to the transmission gate; andan output inverter having an input connected to each of the pass gate, transmission gate, and the pulldown logic, the output inverter also having an output connected to the output node,wherein the exclusive-nor logic circuit is formed by five PMOS transistors and six NMOS transistors. 2. The exclusive-nor logic circuit as recited in claim 1, wherein the pass gate is defined as a PMOS transistor having a gate connected to the output of the second input inverter such that an inverted version of the logic state present at the second input node is received at the gate of the PMOS transistor, and wherein the PMOS transistor has a first terminal connected to the output of the first input inverter and a second terminal connected to the input of the output inverter. 3. The exclusive-nor logic circuit as recited in claim 2, wherein the PMOS transistor is connected to transmit when the logic state at the second input node is high, such that the logic state at the output node is made to match the logic state at the first input node. 4. The exclusive-nor logic circuit as recited in claim 1, wherein the transmission gate is defined by a PMOS transistor and an NMOS transistor which each has a respective first terminal connected to the output of the second input inverter, and which each has a respective second terminal connected to the input of the output inverter, and wherein the NMOS transistor has a gate connected to the first input node, and wherein the PMOS transistor has a gate connected to the output of the first input inverter. 5. The exclusive-nor logic circuit as recited in claim 4, wherein both the NMOS and PMOS transistors are connected to transmit when the logic state at the first input node is high, such that the logic state at the output node is made to match the logic state at the second input node. 6. The exclusive-nor logic circuit as recited in claim 1, wherein the pulldown logic is defined by a first NMOS transistor and a second NMOS transistor, wherein the first and second NMOS transistors are serially connected between a reference ground potential and the input of the output inverter. 7. The exclusive-nor logic circuit as recited in claim 6, wherein a gate of the first NMOS transistor is connected to the output of the second input inverter, and wherein a gate of the second NMOS transistor is connected to the output of the first input inverter. 8. The exclusive-nor logic circuit as recited in claim 6, wherein a gate of the first NMOS transistor is connected to the output of the first input inverter, and wherein a gate of the second NMOS transistor is connected to the output of the second input inverter. 9. The exclusive-nor logic circuit as recited in claim 6, wherein both the first and second NMOS transistors are connected to transmit when the logic states at the first and second input nodes are both low, such that the logic state at the output node is driven high. 10. The exclusive-nor logic circuit as recited in claim 1, wherein the exclusive-nor logic circuit is defined within a semiconductor chip. 11. An exclusive-nor logic circuit layout, comprising: five PMOS transistors; andsix NMOS transistors,wherein the five PMOS transistors are respectively paired with five of the six NMOS transistors such that each pair of PMOS and NMOS transistors is defined to share a contiguous gate electrode structure placed along a respective one of five gate electrode tracks,wherein a sixth of the six NMOS transistors is defined by a gate electrode structure placed along a sixth gate electrode track, such that the sixth NMOS transistor does not share the sixth gate electrode track with another transistor within the exclusive-nor logic circuit layout, andwherein the six gate electrode tracks are oriented parallel to each other. 12. The exclusive-nor logic circuit layout as recited in claim 11, wherein the exclusive-nor logic circuit layout is devoid of co-linearly placed gate electrodes having and end-to-end spacing therebetween. 13. The exclusive-nor logic circuit layout as recited in claim 11, wherein each gate electrode structure is defined an a linear structure having a substantially rectangular cross-section when viewed in an as-drawn state. 14. The exclusive-nor logic circuit layout as recited in claim 11, wherein the six gate electrode tracks are equally spaced apart. 15. The exclusive-nor logic circuit layout as recited in claim 11, wherein the exclusive-or logic circuit layout is recorded in a digital format on a computer readable medium. 16. The exclusive-nor logic circuit layout as recited in claim 15, wherein the digital format is a data file format for storing and communicating one or more semiconductor device layouts. 17. The exclusive-nor logic circuit layout as recited in claim 15, wherein the computer readable medium includes program instructions for accessing and retrieving the exclusive-nor logic circuit layout in the digital format from the computer readable medium. 18. The exclusive-nor logic circuit layout as recited in claim 17, wherein the program instructions for accessing and retrieving include program instructions for selecting a library, a cell, or both library and cell including the exclusive-nor logic circuit layout in the digital format. 19. A method for creating a layout of an exclusive-nor logic integrated circuit, comprising: operating a computer to define a layout of a first input node;operating the computer to define a layout of a second input node;operating the computer to define a layout of an output node;operating the computer to define a layout of a pass gate connected to be controlled by a logic state present at the second input node, the pass gate connected to pass through a version of a logic state present at the first input node to the output node when controlled to transmit by the logic state present at the second input node;operating the computer to define a layout of a transmission gate connected to be controlled by the logic state present at the first input node, the transmission gate connected to pass through a version of the logic state present at the second input node to the output node when controlled to transmit by the logic state present at the first input node; andoperating the computer to define a layout of pulldown logic connected to be controlled by both the logic state present at the first input node and the logic state present at the second input node, the pulldown logic connected to drive a state present at the output node high when both the logic state present at the first input node and the logic state present at the second input node are low;operating the computer to define a layout of a first input inverter having an input connected to the first input node and an output connected to the pass gate;operating the computer to define a layout of a second input inverter having an input connected to the second input node and an output connected to the transmission gate; andoperating the computer to define a layout of an output inverter having an input connected to each of the pass gate, transmission gate, and the pulldown logic, the output inverter also having an output connected to the output node,wherein the exclusive-nor logic integrated circuit is formed by five PMOS transistors and six NMOS transistors.
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