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Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/00
  • G01R-031/3185
  • G01R-031/26
  • G11C-029/32
  • G01R-031/3177
출원번호 US-0084553 (2016-03-30)
등록번호 US-9696379 (2017-07-04)
발명자 / 주소
  • Buyuktosunoglu, Alper
  • Emma, Philip G.
  • Hartstein, Allan M.
  • Healy, Michael B.
  • Kailas, Krishnan K.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Davis, Jennifer R.
인용정보 피인용 횟수 : 0  인용 특허 : 27

초록

A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restorin

대표청구항

1. A semiconductor device, comprising: a first chip and a second chip, which are physically conjoined to form a vertically stacked structure with vertical connections between the first and second chips;wherein the first chip comprises functional circuitry and memory elements to store system state da

이 특허에 인용된 특허 (27)

  1. Pan, Yu-Tang; Wu, Cheng-Ting; Chou, Shih-Wen; Liu, Hui-Ping, Chip package without core and stacked chip package structure.
  2. Almukhaizim, Sobeeh A.; Sinanoglu, Ozgur, Circuit and method providing dynamic scan chain partitioning.
  3. Makar, Samy; Banerjee, Anuja, Dynamic scan chain grouping.
  4. Campbell, Brian J., Dynamic scan circuitry for B-phase.
  5. Kapur,Rohit; Sitchinava,Nodari; Samaranayake,Samitha; Gizdarski,Emil; Neuveux,Frederic; Duggirala,Suryanarayana; Williams,Thomas W., Dynamically reconfigurable shared scan-in test architecture.
  6. Zhou, Qing A; Lu, Daoqiang; Shi, Wei; He, Jiangqi, Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture.
  7. Mueller Gerhard ; Kirihata Toshiaki ; Hoenigschmid Heinz,DEX, High density semiconductor memory having diagonal bit lines and dual word lines.
  8. Liu, Yong; Luk, Wing Kin; Friedman, Daniel Joseph, Low-swing signaling scheme for data communication.
  9. Norman, Robert, Memory power management.
  10. Xie, Feng; Shantz, Michael J., Method and apparatus for adaptive hierarchical visibility in a tiled three-dimensional graphics architecture.
  11. Chakraborty, Tapan J.; Chiang, Chen-Huan; Goyal, Suresh; Portolan, Michele; Van Treuren, Bradford Gene, Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing.
  12. Luis F. Stevens, Method, system and computer program product for managing memory in a non-uniform memory access system.
  13. Jouppi, Norman Paul, Modular three-dimensional chip multiprocessor.
  14. Tanguay ; Jr. Armand R. (Fullerton CA) Jenkins B. Keith (Long Beach CA), Modulator-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration.
  15. Harris,Shaun L.; Belson,Steven A.; Peterson,Eric C.; Williams,Gary W.; Belady,Christian L., Multi-chip module with stacked redundant power.
  16. Lowden Richard A. ; McCoig Thomas M. ; Dooley Joseph B. ; Smith Cyrus M., Non-lead, environmentally safe projectiles and explosives containers.
  17. Lee, Jong-Joo, Planar multi semiconductor chip package and method of manufacturing the same.
  18. Woods,Paul Richard; McDougal,Jay Dean, Scan-based state save and restore method and system for inactive state power reduction.
  19. Huisman,Leendert M.; Pastel,Leah M. P., Segmented scan chains with dynamic reconfigurations.
  20. Crouch Alfred L. (Austin TX) Pressly Matthew D. (Austin TX) Circello Joseph C. (Phoenix AZ) Duerden Richard (Scottsdale AZ), Serial scan chain architecture for a data processing system and method of operation.
  21. Carson John C. (Corona del Mar CA) DeCaro Robert E. (San Juan Capistrano CA) Hsu Ying (Huntington Beach CA) Miyake Michael K. (Westminster CA), Stackable modules and multimodular assemblies.
  22. Lung, Hsiang-Lan, Stacked bit line dual word line nonvolatile memory.
  23. Segelken John M. (Morristown NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY) Wu Lesley J. (Denville NJ), Stacked board assembly for computing machines, including routing boards.
  24. Welch, M. Jason; Nuber, Paul D, System and method for dynamic modification of integrated circuit functionality.
  25. Farrar,Paul A., Three-dimensional multichip module.
  26. Pearson, Eric C., Tiled memory array for full search motion estimation.
  27. Leigh Anthony W. (Houston TX), Two-port two-transistor DRAM.
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