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Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising

Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal. The device includes a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal. The device includes a first load connected to a drain of the third transistor. The device includes a second load connected to a drain of the fourth transistor. The device includes at least one capacitor connected in parallel between the first load and the second load.

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1. A device, comprising: a first terminal connected to an input line, the first terminal to receive an input signal through the input line;a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first

1. A device, comprising: a first terminal connected to an input line, the first terminal to receive an input signal through the input line;a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal;a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal;a first load connected to a drain of the third transistor;a second load connected to a drain of the fourth transistor;at least one capacitor connected in parallel between the first load and the second load;a second terminal connected to the input line, and wherein a gate of the fourth transistor is connected to the second terminal; anda third differential pair of transistors comprising a fifth transistor and a sixth transistor, wherein a gate of the fifth transistor is connected to the second terminal, wherein the transistors are n-channel metal oxide semiconductor (nmos) transistors, and wherein the first load and the second load each have a transconductance that is one-half of a transconductance of a third load and a fourth load. 2. The device of claim 1, further comprising: a third load connected to a drain of the first transistor, wherein the drain of the first transistor is connected to a drain of the fifth transistor;a third terminal connected to the drain of the first transistor, wherein the third terminal provides an output signal;a fourth load connected to a drain of the sixth transistor; anda fourth terminal connected to the drain of the sixth transistor, wherein the fourth terminal provides the output signal, and wherein the drain of the sixth transistor is connected to a drain of the second transistor. 3. The device of claim 1, further comprising: a delay unit connected in parallel between the drain of the third transistor and the drain of the fourth transistor, the delay unit including a plurality of parallel lines with each of the plurality of parallel lines including at least one capacitor connected in series with a transistor. 4. The device of claim 2, wherein the first load, the second load, the third load and the fourth load are transistors connected to a voltage source, and wherein the device provides continuous-time delay of the input signal. 5. The device of claim 2, wherein the first terminal and the second terminal receive the input signal in opposing polarities, and wherein the third terminal and the fourth terminal provide the output signal in opposing polarities. 6. The device of claim 1, wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, a source of the fourth transistor, a source of the fifth transistor, and a source of the sixth transistor are connected DC bias current generators. 7. An apparatus, comprising: filter logic configured to adjust an analog signal to produce an adjusted signal according to a timing variable configured by a delay unit, wherein the timing variable is a ratio between (i) a total capacitance of connected capacitors in the delay unit and (ii) a transconductance of transistors in the delay unit, wherein a first capacitor is connected between a first transistor and a second transistor and, wherein the ratio is based at least in part on a first capacitance of the first capacitor and a first transconductance of the first transistor; anddifferential logic configured to subtract the analog signal from the adjusted signal to generate, in continuous-time, an output signal with a time delay that is a function of the timing variable,wherein the delay unit includes delay logic configured to dynamically modify the total capacitance to change the timing variable and a resulting time delay by which the analog signal is adjusted. 8. The apparatus of claim 7, the delay unit comprising: an array of capacitors connected in parallel, wherein each capacitor has an associated capacitance; andthe delay logic connected to the array of capacitors and configured to individually activate capacitors in the array to dynamically modify the timing variable, wherein the delay logic is configured to selectively activate capacitors as a function of a control signal. 9. The apparatus of claim 7, wherein the delay logic is configured to dynamically modify the total capacitance to change the ratio and the resulting time delay by which the analog signal is adjusted. 10. The apparatus of claim 7, wherein the apparatus is a high speed wire-line communication device and the analog signal is a communication signal processed by the high speed wire-line communication device. 11. The apparatus of claim 7, wherein the apparatus is a hard-disk drive and the analog signal is a signal in a read channel of the hard-disk drive. 12. A method, comprising: adjusting an analog signal to produce an adjusted signal according to a timing variable, wherein the timing variable is a ratio between (i) a total capacitance of connected capacitors and (ii) a transconductance of transistors, wherein a first capacitor of the connected capacitors is connected between a first transistor of the transistors and a second transistor of the transistors and, wherein the ratio is based at least in part on a first capacitance of the first capacitor and a first transconductance of the first transistor;subtracting the analog signal from the adjusted signal to generate an output signal with a time delay that is a function of the timing variable; anddynamically modifying the total capacitance to change the timing variable and a resulting time delay by which the analog signal is adjusted. 13. The method of claim 12, wherein dynamically modifying the total capacitance includes individually activating capacitors in a parallel array of capacitors to dynamically modify the total capacitance as a function of a control signal. 14. The method of claim 13, wherein dynamically modifying the total capacitance changes the ratio and the resulting time delay by which the analog signal is adjusted. 15. The method of claim 12, wherein the adjusting is performed by a circuit that is connected to a high speed wire-line communication device, and wherein the analog signal is a communication signal. 16. The method of claim 12, wherein the adjusting is performed by a circuit that is connected to a hard-disk drive, and wherein the analog signal is a signal in a read channel of the hard-disk drive.