Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/822
H01L-021/84
H01L-021/683
H01L-023/00
H01L-023/525
H01L-023/544
H01L-025/065
H01L-027/02
H01L-027/092
H01L-027/10
H01L-027/105
H01L-027/108
H01L-027/115
H01L-027/118
H01L-029/66
H01L-029/423
H01L-029/78
G06F-017/50
H01L-021/762
H01L-021/8238
H01L-025/00
H01L-027/06
H01L-027/11
H01L-027/112
H01L-027/11526(2017.01)
H01L-027/11529(2017.01)
H01L-027/11551(2017.01)
H01L-027/11573(2017.01)
H01L-027/11578(2017.01)
H01L-027/12
H01L-029/788
H01L-029/792
H01L-023/367
H01L-023/48
출원번호
US-0970602
(2010-12-16)
등록번호
US-9711407
(2017-07-18)
발명자
/ 주소
Or-Bach, Zvi
Cronquist, Brian
Beinglass, Israel
de Jong, J. L.
Sekar, Deepak C.
Lim, Paul
출원인 / 주소
Monolithic 3D Inc.
대리인 / 주소
Tran & Associates
인용정보
피인용 횟수 :
3인용 특허 :
310
초록▼
A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, t
A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
대표청구항▼
1. A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate and a metal layer, said metal layer comprising a majority of aluminum of copper, andthen transferring a first mono-crystalline layer on top of said metal layer,where
1. A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate and a metal layer, said metal layer comprising a majority of aluminum of copper, andthen transferring a first mono-crystalline layer on top of said metal layer,wherein said metal layer is in-between said, base wafer and said first mono-crystalline layer, and said transferring said first mono-crystalline layer comprises an ion-cut, andsubsequently to said transferring, processing said first mono-crystalline layer to define first transistors,wherein said processing comprises at least two etch steps respectively defining an isolation for said first transistors and defining gates of said first transistors,and wherein the method further comprises connecting said first transistors, thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate. 2. The method according to claim 1, wherein said first transistors are substantially horizontally orientated transistors. 3. The method according to claim 1, wherein said first transistors are junction-less transistors. 4. The method according to claim 1, wherein said first transistors comprise at least one FinFet transistor. 5. The method according to claim 1, wherein at least one of said first transistors has a side gate. 6. The method according to claim 1, wherein said first transistors comprise at least one p-type transistor and one n-type transistor. 7. A method of manufacturing a semiconductor wafer, the method comprising: proving a base wafer comprising a semiconductor substrate comprising first transistors and a metal layer, said metal layer comprising a majority of aluminum or copper, andthen transferring a first mono-crystalline layer on top of said metal layer,wherein said metal layer is in-between said base wafer and said first mono-crystalline layer, andsaid transferring said first mono-crystalline layer comprises and ion-cut, andsubsequently to said transferring, processing said first mono-crystalline layer to define second transistors,wherein said processing comprising at least two etch steps respectively defining an isolation for said second transistors and defining gates of said second transistors,and wherein the method further comprises connecting said first transistors thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate. 8. The method according to claim 7, wherein said second transistors comprise at least one FinFet transistor. 9. The method according to claim 7, wherein at least one of said second transistors has a side gate. 10. The method according to claim 7, wherein said second transistors comprise at least one p-type transistor and one n-type transistor. 11. The method according to claim 7, wherein said second transistors are junction-less transistors. 12. A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate and a metal layer, said metal layer comprising a majority of aluminum or copper, andthen transferring a first mono-crystalline layer on top of said metal layer,wherein said metal layer is in-between said base wafer and said first mono-crystalline layer, andsaid transferring said first mono-crystalline layer comprising an ion-cut, andsubsequently to said transferring, processing said first mono-crystalline layer to define first transistors,wherein said processing comprises at least two etch steps respectively defining an isolation for said first transistors and defining gates of said first transistors, andwherein said first transistors comprise at least one FinFet transistor,and wherein the method further comprises connecting said first transistors thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate. 13. The method according to claim 12, wherein said first transistors comprise at least one p-type transistor and one n-type transistor. 14. The method according to claim 12, wherein an optical anneal is performed after said ion-cut to repair damage from said ion-cut. 15. The method according to claim 12, wherein said first transistors are high k metal gate (HKMG) transistors. 16. The method according to claim 12, wherein said first mono-crystalline layer is less than 1 micron thick. 17. The method according to claim 12, wherein said first transistors are substantially horizontally orientated transistors. 18. The method according to claim 12, wherein at least one of said first transistors has a side gate.
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Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Michael Mark W. ; Moore Bradley T. ; Wristers Derick J., Method and apparatus for in situ anneal during ion implant.
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Mazur Carlos A. (Austin TX) Fitch Jon T. (Austin TX) Hayden James D. (Austin TX) Witek Keith E. (Austin TX), Semiconductor memory device and method of formation.
Zavracky Paul M. (Norwood MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert (Norwell MA) Jacobsen Jeffrey (Hollister CA) Dingle Brenda (Norton MA) Spitzer Mark B. (Sharon MA), Single crystal silicon arrayed devices for display panels.
Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.
Atkinson Gary M. (1012 - 7th St. ; #15 Santa Monica CA 90403) Courtney M. DuChesne (15127 Blackhawk Mission Hills CA 91345), Split collector vacuum field effect transistor.
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Barbee Steven G. (Dover Plains NY) Leas James M. (Washington DC) Lloyd James R. (Fishkill NY) Nagarajan Arunachala (Wappingers Falls NY), Thin film semiconductor device and method for manufacture.
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