초록 ▼

A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed

A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.

대표청구항 ▼

1. A semiconductor device comprising: a first package comprising: a laminate layer;an overmold layer above and in direct contact with the laminate layer;a logic circuit-through-silicon via (TSV) layer including a logic die and a plurality of TSVs, the logic circuit-TSV layer within the overmold laye

1. A semiconductor device comprising: a first package comprising: a laminate layer;an overmold layer above and in direct contact with the laminate layer;a logic circuit-through-silicon via (TSV) layer including a logic die and a plurality of TSVs, the logic circuit-TSV layer within the overmold layer, the TSVs electrically exposed at a top surface of the overmold layer;a plurality of solder bumps electrically connecting the logic circuit-TSV layer to the laminate layer within the overmold layer;an underfill layer within the overmold layer between the logic circuit-TSV layer and the laminate layer, within which the solder bumps are disposed, the underfill layer being a different layer than the overmold layer, the underfill layer being of a different material than the overmold layer; anda plurality of through-mold vias (TMVs) within the overmold layer to one or more sides of the logic circuit-TSV layer, the TMVs filled with metal, a top surface of the TMVs coplanar with a top surface of the TSVs;a second package comprising an additional logic die; anda connecting layer between a bottom surface of the second package and a top surface of the first package, the top surface of the first package coplanar with the top surface of the TMVs and the top surface of the TSVs, a plurality of solder balls disposed within the connecting layer, the solder balls electrically connecting the second package to the TSVs and the TMVs of the first package. 2. The semiconductor device of claim 1, further comprising a plurality of solder balls on a bottom surface of the laminate layer. 3. The semiconductor device of claim 1, wherein the logic die of the first package comprises a processor, and the additional logic die of the second package comprises memory. 4. The semiconductor device of claim 1, wherein the TMVs each have a profile that tapers downwards from a top of the overmold layer to a bottom of the overmold layer. 5. The semiconductor device of claim 1, wherein the solder balls of the connecting layer do not extend into the first package. 6. The semiconductor device of claim 1, wherein the solder balls of the connecting layer do not extend into the TMVs of the first package.