최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0995483 (2016-01-14) |
등록번호 | US-9741719 (2017-08-22) |
발명자 / 주소 |
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출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 1 인용 특허 : 551 |
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structur
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
1. An integrated circuit, comprising: a first gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in a first direction and that has a lengthwise centerline oriented in the first direction, the substantially linear-shaped portion of the f
1. An integrated circuit, comprising: a first gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in a first direction and that has a lengthwise centerline oriented in the first direction, the substantially linear-shaped portion of the first gate electrode level conductive structure forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first transistor of the first transistor type including a first diffusion region of a first diffusion type and a second diffusion region of the first diffusion type, the first transistor of the second transistor type including a first diffusion region of a second diffusion type and a second diffusion region of the second diffusion type;a second gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in the first direction and that has a lengthwise centerline oriented in the first direction, the second gate electrode level conductive structure positioned next to the first gate electrode level conductive structure such that the first diffusion region of the first diffusion type is located between the first gate electrode level conductive structure and the second gate electrode level conductive structure;a third gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in the first direction and that has a lengthwise centerline oriented in the first direction, the third gate electrode level conductive structure positioned next to the first gate electrode level conductive structure such that the first diffusion region of the second diffusion type is located between the first gate electrode level conductive structure and the third gate electrode level conductive structure, the lengthwise centerline of the third gate electrode level conductive structure substantially aligned with the lengthwise centerline of the second gate electrode level conductive structure, the third gate electrode level conductive structure separated from the second gate electrode level conductive structure by a gap having an extent measured in the first direction between the third gate electrode level conductive structure and the second gate electrode level conductive structure; anda local interconnect conductive structure including a first portion and a second portion, the first portion of the local interconnect conductive structure configured to physically contact both the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type, the second portion of the local interconnect conductive structure configured to extend away from the first portion of the local interconnect conductive structure and through the gap that separates the third gate electrode level conductive from the second gate electrode level conductive structure. 2. The integrated circuit as recited in claim 1, wherein the second gate electrode level conductive structure does not form a transistor using the first diffusion region of the first diffusion type. 3. The integrated circuit as recited in claim 2, wherein the third gate electrode level conductive structure does not form a transistor using the first diffusion region of the second diffusion type. 4. The integrated circuit as recited in claim 1, wherein the first portion of the local interconnect conductive structure is substantially centered between the first gate electrode level conductive structure and the second gate electrode level conductive structure in a second direction perpendicular to the first direction, and wherein the first portion of the local interconnect conductive structure is substantially centered between the first gate electrode level conductive structure and the third gate electrode level conductive structure in the second direction perpendicular to the first direction. 5. The integrated circuit as recited in claim 1, wherein the local interconnect conductive structure does not physically contact the first gate electrode level conductive structure, and wherein the local interconnect conductive structure does not physically contact the second gate electrode level conductive structure, and wherein the local interconnect conductive structure does not physically contact the third gate electrode level conductive structure. 6. The integrated circuit as recited in claim 1, wherein a width of the first gate electrode level conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a width of the second gate electrode level conductive structure as measured in the second direction, and wherein the width of the first gate electrode level conductive structure as measured in the second direction is substantially equal to a width of the third gate electrode level conductive structure as measured in the second direction. 7. The integrated circuit as recited in claim 1, further comprising: a fourth gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in the first direction and that has a lengthwise centerline oriented in the first direction, the substantially linear-shaped portion of fourth gate electrode level conductive structure positioned next to both the substantially linear-shaped portion of the second gate electrode level conductive structure and the substantially linear-shaped portion of the third gate electrode level conductive structure. 8. The integrated circuit as recited in claim 7, wherein a distance as measured in a second direction perpendicular to the first direction between the lengthwise centerline of the substantially linear-shaped portion of the first gate electrode level conductive structure and the lengthwise centerline of the substantially linear-shaped portion of the second gate electrode level conductive structure is substantially equal to a gate electrode pitch, and wherein a distance as measured in the second direction between the lengthwise centerline of the substantially linear-shaped portion of the second gate electrode level conductive structure and the lengthwise centerline of the substantially linear-shaped portion of the fourth gate electrode level conductive structure is substantially equal to the gate electrode pitch. 9. The integrated circuit as recited in claim 7, wherein the second portion of the local interconnect conductive structure is configured to physically contact the fourth gate electrode level conductive structure. 10. The integrated circuit as recited in claim 9, wherein the second portion of the local interconnect conductive structure is configured to extend over a sidewall spacer of the fourth gate electrode level conductive structure to physically contact the fourth gate electrode level conductive structure. 11. The integrated circuit as recited in claim 9, wherein the local interconnect conductive structure that includes the first portion and the second portion is a first local interconnect conductive structure, the integrated circuit further including a second local interconnect conductive structure configured to physically contact the second diffusion region of the first diffusion type. 12. The integrated circuit as recited in claim 11, further comprising: a third local interconnect conductive structure configured to physically contact the second diffusion region of the second diffusion type. 13. The integrated circuit as recited in claim 12, wherein the second local interconnect conductive structure is electrically connected to a power supply, and wherein the third local interconnect conductive structure is electrically connected to a reference ground potential. 14. The integrated circuit as recited in claim 12, further comprising: a first interconnect level conductive structure configured to include a substantially linear-shaped portion that extends in a second direction perpendicular to the first direction and that has a lengthwise centerline oriented in the second direction; anda first contact conductive structure configured to physically contact both the first interconnect level conductive structure and the second local interconnect conductive structure. 15. The integrated circuit as recited in claim 14, further comprising: a second interconnect level conductive structure configured to include a substantially linear-shaped portion that extends in the second direction and that has a lengthwise centerline oriented in the second direction; anda second contact conductive structure configured to physically contact both the second interconnect level conductive structure and the third local interconnect conductive structure. 16. The integrated circuit as recited in claim 15, wherein the first interconnect level conductive structure is electrically connected to a power supply, and wherein the second interconnect level conductive structure is electrically connected to a reference ground potential. 17. The integrated circuit as recited in claim 15, further comprising: a third interconnect level conductive structure configured to include a substantially linear-shaped portion that extends in the second direction and that has a lengthwise centerline oriented in the second direction; anda third contact conductive structure configured to physically contact both the third interconnect level conductive structure and the first gate electrode level conductive structure. 18. The integrated circuit as recited in claim 17, wherein the third interconnect level conductive structure is positioned between the first transistor of the first transistor type and the first transistor of the second transistor type relative to the first direction. 19. The integrated circuit as recited in claim 18, wherein the third interconnect level conductive structure does not extend directly over the first local interconnect conductive structure. 20. The integrated circuit as recited in claim 18, further comprising: a fourth interconnect level conductive structure configured to include a substantially linear-shaped portion that extends in the second direction and that has a lengthwise centerline oriented in the second direction, the fourth interconnect level conductive structure positioned between the first interconnect level conductive structure and the third interconnect level conductive structure relative to the first direction; anda fifth interconnect level conductive structure configured to include a substantially linear-shaped portion that extends in the second direction and that has a lengthwise centerline oriented in the second direction, the fifth interconnect level conductive structure positioned between the fifth interconnect level conductive structure and the third interconnect level conductive structure relative to the first direction. 21. The integrated circuit as recited in claim 20, wherein each of the first interconnect level conductive structure, the second interconnect level conductive structure, the third interconnect level conductive structure, the fourth interconnect level conductive structure, and the fifth interconnect level conductive structure is located within a first interconnect level above a gate electrode level. 22. The integrated circuit as recited in claim 21, wherein the lengthwise centerline of the fourth interconnect level conductive structure is separated from the lengthwise centerline of the first interconnect level conductive structure by a first interconnect level pitch as measured in the first direction, and wherein the lengthwise centerline of the third interconnect level conductive structure is separated from the lengthwise centerline of the fourth interconnect level conductive structure by the first interconnect level pitch as measured in the first direction, andwherein the lengthwise centerline of the fifth interconnect level conductive structure is separated from the lengthwise centerline of the third interconnect level conductive structure by the first interconnect level pitch as measured in the first direction, andwherein the lengthwise centerline of the second interconnect level conductive structure is separated from the lengthwise centerline of the fifth interconnect level conductive structure by the first interconnect level pitch as measured in the first direction. 23. A method for manufacturing an integrated circuit, comprising: forming a first gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in a first direction and that has a lengthwise centerline oriented in the first direction, the substantially linear-shaped portion of the first gate electrode level conductive structure forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first transistor of the first transistor type including a first diffusion region of a first diffusion type and a second diffusion region of the first diffusion type, the first transistor of the second transistor type including a first diffusion region of a second diffusion type and a second diffusion region of the second diffusion type;forming a second gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in the first direction and that has a lengthwise centerline oriented in the first direction, the second gate electrode level conductive structure positioned next to the first gate electrode level conductive structure such that the first diffusion region of the first diffusion type is located between the first gate electrode level conductive structure and the second gate electrode level conductive structure;forming a third gate electrode level conductive structure configured to include a substantially linear-shaped portion that extends in the first direction and that has a lengthwise centerline oriented in the first direction, the third gate electrode level conductive structure positioned next to the first gate electrode level conductive structure such that the first diffusion region of the second diffusion type is located between the first gate electrode level conductive structure and the third gate electrode level conductive structure, the lengthwise centerline of the third gate electrode level conductive structure substantially aligned with the lengthwise centerline of the second gate electrode level conductive structure, the third gate electrode level conductive structure separated from the second gate electrode level conductive structure by a gap having an extent measured in the first direction between the third gate electrode level conductive structure and the second gate electrode level conductive structure; andforming a local interconnect conductive structure including a first portion and a second portion, the first portion of the local interconnect conductive structure configured to physically contact both the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type, the second portion of the local interconnect conductive structure configured to extend away from the first portion of the local interconnect conductive structure and through the gap that separates the third gate electrode level conductive from the second gate electrode level conductive structure.
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