Configurable router for a network on chip (NoC)
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-012/28
H04L-012/24
H04L-012/933
H04L-012/713
H04L-012/721
H04L-012/725
출원번호
US-0493018
(2014-09-22)
등록번호
US-9742630
(2017-08-22)
발명자
/ 주소
Philip, Joji
Kumar, Sailesh
출원인 / 주소
NetSpeed Systems
대리인 / 주소
Procopio, Cory, Hargreaves & Savitch LLP
인용정보
피인용 횟수 :
1인용 특허 :
97
초록▼
Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a Network on Chip (NoC). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership i
Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a Network on Chip (NoC). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership information of the virtual channels, clock domain, and so forth. The router may further be configured to implement arbitration techniques and flit processing techniques based on the parameters specified by the software layer.
대표청구항▼
1. A router in a Network on Chip (NoC) comprising a plurality of routers, the router comprising: a plurality of ports, each of the plurality of ports configured with one or more virtual channels (VCs), each of the one or more VCs associated with a separate buffer, each of the one or more VCs configu
1. A router in a Network on Chip (NoC) comprising a plurality of routers, the router comprising: a plurality of ports, each of the plurality of ports configured with one or more virtual channels (VCs), each of the one or more VCs associated with a separate buffer, each of the one or more VCs configured to connect to specified one or more other ports or VCs of the plurality of ports based on a membership specified by a specification;wherein a number of the plurality of ports and a number of the one or more VCs for the each of the plurality of ports is specified by the specification;wherein a size of each of the one or more VCs and a size of the buffer is specified by the specification;wherein the connectivity between each of the one or more VCs is specified by the specification;wherein the one or more VCs are configured to operate in different clock domain as specified by the specification; wherein said NoC is constructed by a software layer that configures the one or more of the plurality of routers with information from the specification and connects one or more of the plurality of ports of the one or more of the plurality of routers to one another or to one or more agents of the NoC, and that further configures the one or more of the plurality of routers with information to facilitate routing of packets between NoC agents. 2. The router of claim 1, further comprising a controller, wherein the controller is configured to upsize or downsize a flit received at an input one of the one or more VCs and directed to an output one of the one or more VCs based on a size ratio of the input one of the one or more VCs and the output one of the one or more VCs. 3. The router of claim 1, wherein the router is configured to receive a packet at one of the one or more input VCs of one of the one or more input ports comprising a first set having first information for arbitration of the packet and second information for routing of the packet;arbitrate the packet and upon winning the arbitration, perform output VC and output port selection of one of the plurality of output VCs and output ports from the first information;calculate a second set having first information and second information for arbitration and routing of the packet at next NoC router using the first and second information; andforward the second set along with the packet to the next NoC router. 4. The router of claim 3, wherein the first information of the packet is indicative of the output VC and output port at a router and second information of the packet is indicative of one or more turns at one or more routers of the NoC. 5. The router of claim 1, wherein each of the one or more VCs is associated with a Quality of Service (QoS) specified by the specification, wherein the router is configured to conduct arbitration based on the QoS of the one or more VCs. 6. The router of claim 1, wherein each of the one or more VCs is associated with a clock domain specified by the specification, and wherein the router is configured to facilitate clock domain crossing logic for the one or more VCs. 7. The router of claim 1, wherein the router is configured to facilitate independent flow control for each one of the plurality of ports that is connected to another router port or an agent of the NoC. 8. The router of claim 7, wherein the router is configured with flow control information from the specification to facilitate the independent flow control between each one of the plurality of ports of the router and the corresponding another router port or NoC agent connected to the port. 9. The router of claim 1, wherein the router further comprises an output buffering stage for one or more of the plurality of ports specified by the specification. 10. The router of claim 1, wherein the router further comprises a pipeline with one or more stages for one or more of the plurality of ports, the one or more stages and the one or more of the plurality of ports specified by the specification. 11. The router of claim 1, wherein the router is configured to, for each arbitration operation: transmit a number of flits from the one or more input VCs of ones of the plurality of input ports to one or more output VCs of ones of the plurality of output ports; the number of flits specified by the specification. 12. A semiconductor device configured with a Network on Chip (NoC) generated from a specification, the semiconductor device comprising: one or more hosts; anda router, comprising:a plurality of ports, each of the plurality of ports configured with one or more virtual channels (VCs), each of the one or more VCs associated with a separate buffer, each of the one or more VCs configured to connect to specified one or more other ports or VCs of the plurality of ports based on a membership specified by the specification;wherein a number of the plurality of ports and a number of the one or more VCs for the each of the plurality of ports is specified by the specification;wherein a size of each of the one or more VCs and a size of the buffer is specified by the specification;wherein the connectivity between each of the one or more VCs is specified by the specification;wherein the one or more VCs are configured to operate in different clock domain as specified by the specification;wherein said NoC is constructed by a software layer that configures the one or more of the plurality of routers with information from the specification and connects one or more of the plurality of ports of the one or more of the plurality of routers to one another or to one or more agents of the NoC, and that further configures the one or more of the plurality of routers with information to facilitate routing of packets between NoC agents. 13. The semiconductor device of claim 12, wherein the router comprises a controller, wherein the controller is configured to upsize or downsize a flit received at an input one of the one or more VCs and directed to an output one of the one or more VCs, based on a size ratio of the input one of the one or more VCs and the output one of the one or more VCs. 14. The semiconductor device of claim 12, wherein the router is configured to: receive a packet at one of the one or more input VCs of one of the one or more input ports comprising a first set having first information for arbitration of the packet and second information for routing of the packet;arbitrate the packet and upon winning the arbitration, perform output VC and output port selection of one of the plurality of output VCs and output ports from the first information;calculate a second set having first information and second information for arbitration and routing of the packet at next NoC router using the first and second information; andforward the second set along with the packet to the next NoC router. 15. The semiconductor device of claim 14, wherein the first information of the packet is indicative of the output VC and output port at a router, and wherein the second information of the packet is indicative of one or more turns at one or more routers of the NoC. 16. The semiconductor device of claim 12, wherein each of the one or more VCs is associated with a Quality of Service (QoS) specified by the specification, wherein the router is configured to conduct arbitration based on the QoS of the one or more VCs. 17. The semiconductor device of claim 12, wherein each of the one or more VCs is associated with a clock domain specified by the specification, and wherein the router is configured to facilitate clock domain crossing logic for the one or more VCs. 18. The semiconductor device of claim 12, wherein the router is configured to facilitate independent flow control for each one of the plurality of ports that is connected to another router port or an agent of the NoC.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (97)
Or-Bach, Zvi; Wurman, Ze'ev, 3D integrated circuit with logic.
Hahn Jong Seok,KRX ; Sim Won Sae,KRX ; Hahn Woo Jong,KRX ; Yoon Suk Han,KRX, Adaptive routing controller of a crossbar core module used in a crossbar routing switch.
Dapp Michael C. (Endwell NY) Barker Thomas N. (Vestal NY) Dieffenderfer James W. (Owego NY) Knowles Billy J. (Kingston NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Rolfe David , Advanced parallel processor including advanced support hardware.
Miller,Ian D.; Harris,Jonathan C., Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages.
Agrawal Rakesh ; Gehrke Johannes Ernst ; Gunopulos Dimitrios ; Raghavan Prabhakar, Automatic subspace clustering of high dimensional data for data mining applications.
Muff, Adam J.; Schardt, Paul E.; Shearer, Robert A.; Tubbs, Matthew R., Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core.
Thubert, Pascal; Le Faucheur, Francois Laurent; Levy-Abegnoli, Eric M., Forwarding packets to a directed acyclic graph destination using link selection based on received link metrics.
Flaig Charles M. (Pasadena CA) Seitz Charles L. (San Luis Rey CA), Inter-computer message routing system with each computer having separate routinng automata for each dimension of the net.
Fuhrmann Amir Michael ; Rakib Selim Shlomo ; Azenkot Yehuda, Lower overhead method for data transmission using ATM and SCDMA over hybrid fiber coax cable plant.
Hilgendorf Rolf B. (Boeblingen DEX) Schlipf Thomas (Holzgerlingen DEX), Method and apparatus for avoiding deadlock in a computer system with two or more protocol-controlled buses interconnecte.
Okhmatovski, Vladimir; Yuan, Mengtao; Phelps, Rodney, Method and apparatus for broadband electromagnetic modeling of three-dimensional interconnects embedded in multilayered substrates.
Williams, Jr., John J.; Dejanovic, Thomas; Michelson, Jonathan E., Method and apparatus for using barrier phases to limit packet disorder in a packet switching system.
James David V. ; North Donald N. ; Stone Glen D., Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system.
Levin Vladimir K.,RUX ; Karatanov Vjacheslav V.,RUX ; Jalin Valerii V.,RUX ; Titov Alexandr,RUX ; Agejev Vjacheslav M.,RUX ; Patrikeev Andrei,RUX ; Jablonsky Sergei V.,RUX ; Korneev Victor V.,RUX ; M, Method for deadlock-free message passing in MIMD systems using routers and buffers.
Kalmanek, Jr., Charles Robert; Lauck, Anthony G; Ramakrishnan, Kadangode K., Method for determining non-broadcast multiple access (NBMA) connectivity for routers having multiple local NBMA interfaces.
Bruce,Alistair Crone; Mathewson,Bruce James; Harris,Antony John, Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus.
Kodialam, Muralidharan S.; Lakshman, Tirnuell V.; Sengupta, Sudipta, Multicast routing with service-level guarantees between ingress egress-points in a packet network.
Hoover, Russell D.; Kriegel, Jon K.; Mejdrich, Eric O.; Shearer, Robert A., Network on chip with a low latency, high bandwidth application messaging interconnect.
Mejdrich, Eric O.; Schardt, Paul E.; Shearer, Robert A.; Tubbs, Matthew R., Performance event triggering through direct interthread communication on a network on chip.
Koza John R. ; Andre David ; Tackett Walter Alden, Simultaneous evolution of the architecture of a multi-part program while solving a problem using architecture altering operations.
Pleshek, Ronald A.; Webb, III, Charles A.; Cheney, Keith E.; Hilton, Gregory S.; Abkowitz, Patricia A.; Thakkar, Arun K.; Thaker, Himanshu M., Superset packet forwarding for overlapping filters and related systems and methods.
Prasad,Roy V.; Horng,Chi Song; Ramanujam,Ram S., System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections.
Birrittella Mark S. (Chippewa Falls WI) Kessler Richard E. (Eau Claire WI) Oberlin Steven M. (Chippewa Falls WI) Passint Randal S. (Chippewa Falls WI) Thorson Greg (Altoona WI), System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic.
Jayasimha, Doddaballapur N.; Chan, Jeremy; Tomlinson, Jay S., Use of common data format to facilitate link width conversion in a router with flexible link widths.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.