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A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectivel

A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

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1. A data processing system comprising: a software plane comprising two or more host components having respective central processing units configured to execute machine-readable instructions;a hardware acceleration plane comprising two or more hardware acceleration components; anda common network co

1. A data processing system comprising: a software plane comprising two or more host components having respective central processing units configured to execute machine-readable instructions;a hardware acceleration plane comprising two or more hardware acceleration components; anda common network configured to allow the two or more host components to communicate with each other, and to allow the two or more hardware acceleration components to communicate with each other,a first host component of the data processing system or a first hardware acceleration component associated with the first host component being configured to obtain an address of a specific hardware acceleration component that is configured to perform a requested service,the first hardware acceleration component being configured to: when the address identifies the first hardware acceleration component as the specific hardware acceleration component that is configured to perform the requested service, locally perform the requested service on the first hardware acceleration component, andwhen the address identifies a second hardware acceleration component as the specific hardware acceleration component that is configured to perform the requested service, route the request to the second hardware acceleration component via the common network without involvement of the first host component,the two or more hardware acceleration components in the hardware acceleration plane having parallel logic elements configured to perform computations to obtain intermediate results or final results of various services including the requested service, the two or more hardware acceleration components being configured to communicate the intermediate results or the final results of the various services to other hardware acceleration components in the hardware acceleration plane without assistance from the software plane. 2. The data processing system of claim 1, wherein said two or more hardware acceleration components in the hardware acceleration plane correspond to field-programmable gate array (FPGA) devices. 3. The data processing system of claim 1, wherein said two or more host components in the software plane exchange packets over the common network via a first logical network,wherein said two or more hardware acceleration components in the hardware acceleration plane exchange packets over the common network via a second logical network, andwherein the first logical network and the second logical network share physical links of the common network and are distinguished from each other based on classes of traffic to which their respective packets pertain. 4. The data processing system of claim 3, wherein packets sent over the second logical network use a specified protocol on an identified port, which constitutes a characteristic that distinguishes packets sent over the second logical network from packets sent over the first logical network. 5. The data processing system of claim 1, further comprising plural server unit components, each server unit component comprising: a local host component;a local hardware acceleration component; anda local physical link coupling the local host component with the local hardware acceleration component,the local hardware acceleration component being coupled to the common network, and serving as a conduit by which the local host component communicates with the common network. 6. The data processing system of claim 5, wherein at least one server unit component includes plural local host components and/or plural local hardware acceleration components. 7. The data processing system of claim 5, wherein the local hardware acceleration component is coupled to a top-of-rack switch in a data center. 8. The data processing system of claim 5, wherein the local hardware acceleration component is also coupled to a network interface controller, andwherein the network interface controller is coupled to the local host component. 9. The data processing system of claim 5, the plural server unit components including a first server unit component that includes the first host component and the first hardware acceleration component and a second server unit component that includes a second host component and the second hardware acceleration component. 10. The data processing system of claim 1, an individual host component being configured to determine the address in response to a request for the requested service and send the address to the first hardware acceleration component. 11. A method for performing a service in a data processing environment comprising plural host components coupled to plural hardware acceleration components, the method comprising: in a local host component or in a local hardware acceleration component that is coupled to the local host component: issuing a request for the service; andreceiving a reply to the request which identifies an address of a specific hardware acceleration component that is configured to perform the service; andin the local hardware acceleration component: when the address identifies the local hardware acceleration component as the specific hardware acceleration component that is configured to perform the service: locally performing the service on the local hardware acceleration component using parallel logic elements of the local hardware acceleration component, andoutputting, over a common network, intermediate or final results that are responsive to the request to a remote hardware acceleration component without involvement of the local host component; andwhen the address identifies the remote hardware acceleration component as the specific hardware acceleration component that is configured to perform the service, routing the request to the remote hardware acceleration component, the remote hardware acceleration component using other parallel logic elements to output the intermediate or final results that are responsive to request to the local hardware acceleration component,wherein the plural host components have respective processing units configured to execute instructions,wherein the plural host components communicate with each other in the data processing environment over the common network, andwherein the plural hardware acceleration components communicate with each other in the data processing environment over the common network. 12. The method of claim 11, wherein the local hardware acceleration component is a field-programmable gate array (FPGA) device. 13. The method of claim 11, wherein the common network supports a first logical network and a second logical network that share physical links of the common network, the method further comprising: causing the plural host components in the data processing environment to use the first logical network to exchange packets with each other using a particular class of network traffic; andcausing the plural hardware acceleration components in the data processing environment to use the second logical network to exchange other packets with each other using another class of network traffic. 14. The method of claim 13, wherein the other packets sent over the second logical network use a specified protocol on an identified port, which constitutes a characteristic that distinguishes the other packets sent over the second logical network from the packets sent over the first logical network. 15. The method of claim 11, wherein the local hardware acceleration component is an application-specific integrated circuit. 16. The method of claim 15, wherein the local hardware acceleration component is coupled to a top-of-rack switch in a data center, the method comprising: sending the intermediate or final results from the local hardware acceleration component, through the top-of-rack switch, and over the common network. 17. A server unit component comprising: a local host component that uses one or more central processing units to execute machine-readable instructions;a local hardware acceleration component having parallel logic elements; anda local physical link configured to couple the local host component with the local hardware acceleration component,the local hardware acceleration component being configured to couple to a common network and configured to serve as a conduit by which the local host component communicates with the common network in a data processing environment having respective other server unit components, the respective other server unit components comprising respective other host components and respective other hardware acceleration components with respective other parallel logic elements, the local host component, the local hardware acceleration component, the respective other host components, and the respective other hardware acceleration components being configured to perform various services,the local host component or the local hardware acceleration component being configured to determine an address of a specific hardware acceleration component that is configured to perform a requested service,the local hardware acceleration component being configured to: when the address identifies the local hardware acceleration component as the specific hardware acceleration component that is configured to perform the requested service, locally perform the requested service on the local hardware acceleration component, andwhen the address identifies another hardware acceleration component as the specific hardware acceleration component that is configured to perform the requested service, route the request to the another hardware acceleration component via the common network without involvement of the local host component,the local hardware acceleration component having parallel logic elements configured to perform computations to obtain intermediate results or final results of the requested service, andthe local hardware acceleration component being configured to communicate the intermediate results or the final results of the requested service to a further hardware acceleration component over the common network without assistance from the local host component. 18. The server unit component of claim 17, wherein the server unit component includes plural local host components and/or plural local hardware acceleration components. 19. The server unit component of claim 17, wherein the local hardware acceleration component is coupled to a top-of-rack switch in a data center. 20. The server unit component of claim 17, wherein the local hardware acceleration component and the local host component are configured to communicate over the common network using network traffic with different characteristics such that communications by the local hardware acceleration component are received by other hardware acceleration components and other communications by the local host component are received by other host components.