최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0064323 (2016-03-08) |
등록번호 | US-9818747 (2017-11-14) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 574 |
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask fil
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.
1. A semiconductor device, comprising: a first gate structure including a central conductive region and sidewall spacers disposed on side surfaces of the central conductive region, the first gate structure including a portion that forms a gate electrode of a transistor;a second gate structure includ
1. A semiconductor device, comprising: a first gate structure including a central conductive region and sidewall spacers disposed on side surfaces of the central conductive region, the first gate structure including a portion that forms a gate electrode of a transistor;a second gate structure including a central conductive region and sidewall spacers disposed on side surfaces of the central conductive region, the second gate structure including a portion positioned over a shallow trench isolation region and next to the portion of the first gate structure that forms the gate electrode of the transistor;an active area formed within a substrate between the central conductive region of the first gate structure and the shallow trench isolation region over which the second gate structure is positioned;an active area contact structure positioned between the first gate structure and the second gate structure, the active area contact structure in contact with the active area; anda photon absorption material disposed between the first gate structure and the second gate structure and around the active area contact structure, the photon absorption material providing a minimal backscattering of photons incident upon a surface of the photon absorption material. 2. The semiconductor device as recited in claim 1, wherein the active area contact structure is positioned a first distance away from a nearest location of a nearest sidewall spacer of the first gate structure, and wherein the active area contact structure is positioned a second distance away from a nearest location of a nearest sidewall spacer of the second gate structure, and wherein the first distance and the second distance are substantially equal. 3. The semiconductor device as recited in claim 2, wherein the photon absorption material is disposed between the active area contact structure and the nearest sidewall spacer of the first gate structure, and wherein the photon absorption material is disposed between the active area contact structure and the nearest sidewall spacer of the second gate structure. 4. The semiconductor device as recited in claim 1, wherein the active area formed within a substrate is an n+ active area. 5. The semiconductor device as recited in claim 4, further comprising: a p-well region formed below the first gate structure and below the active area, the p-well region extending to the shallow trench isolation region over which the portion of the second gate structure is positioned. 6. The semiconductor device as recited in claim 1, wherein the active area formed within a substrate is an p+ active area. 7. The semiconductor device as recited in claim 6, further comprising: an n-well region formed below the first gate structure and below the active area, the n-well region extending to the shallow trench isolation region over which the portion of the second gate structure is positioned. 8. The semiconductor device as recited in claim 1, wherein the first gate structure has a substantially linear shape defined by a length and a width, the length of the first gate structure extending in a first direction and the width of the first gate structure extending in a second direction perpendicular to the first direction, the length of the first gate structure measured along a centerline of the first gate structure from a first end of the first gate structure to a second end of the first gate structure, the centerline of the first gate structure extending through a midpoint of the width of the first gate structure, the width of the first gate structure measured at a location halfway along the length of the first gate structure, and wherein the second gate structure has a substantially linear shape defined by a length and a width, the length of the second gate structure extending in the first direction and the width of the second gate structure extending in the second direction perpendicular to the first direction, the length of the second gate structure measured along a centerline of the second gate structure from a first end of the second gate structure to a second end of the second gate structure, the centerline of the second gate structure extending through a midpoint of the width of the second gate structure, the width of the second gate structure measured at a location halfway along the length of the second gate structure. 9. The semiconductor device as recited in claim 8, wherein the length of the first gate structure is substantially equal to the length of the second gate structure. 10. The semiconductor device as recited in claim 9, wherein both the first end of the first gate structure and the first end of the second gate structure are positioned at a same virtual line extending in the second direction. 11. The semiconductor device as recited in claim 10, wherein the transistor with its gate electrode formed by the portion of the first gate structure is a first transistor of a first transistor type, and wherein the active area is a first active area, and wherein the active area contact is a first active area contact, and wherein the first gate structure also includes a portion that forms a gate electrode of a first transistor of a second transistor type, the first transistor of the first transistor type separated from the first transistor of the second transistor type by an inactive region of the substrate. 12. The semiconductor device as recited in claim 11, wherein the second gate structure includes a second portion positioned over the shallow trench isolation region and next to the portion of the first gate structure that forms the gate electrode of the first transistor of the second transistor type, the semiconductor device including a second active area formed within the substrate between the central conductive region of the first gate structure and the shallow trench isolation region over which the second portion of the second gate structure is positioned. 13. The semiconductor device as recited in claim 12, further comprising: a second active area contact structure positioned between the first gate structure and the second gate structure, the second active area contact structure in contact with the second active area; anda photon absorption material disposed between the first gate structure and the second gate structure and around the second active area contact structure. 14. The semiconductor device as recited in claim 13, wherein the first active area contact structure is positioned a first distance away from a nearest location of a nearest sidewall spacer of the first gate structure, and wherein the first active area contact structure is positioned a second distance away from a nearest location of a nearest sidewall spacer of the second gate structure, and wherein the first distance and the second distance are substantially equal, and wherein the second active area contact structure is positioned the first distance away from a nearest location of a nearest sidewall spacer of the first gate structure, and wherein the second active area contact structure is positioned the second distance away from a nearest location of a nearest sidewall spacer of the second gate structure. 15. The semiconductor device as recited in claim 14, wherein the photon absorption material is disposed between the first active area contact structure and the nearest sidewall spacer of the first gate structure, and wherein the photon absorption material is disposed between the first active area contact structure and the nearest sidewall spacer of the second gate structure, and wherein the photon absorption material is disposed between the second active area contact structure and the nearest sidewall spacer of the first gate structure, and wherein the photon absorption material is disposed between the second active area contact structure and the nearest sidewall spacer of the second gate structure. 16. The semiconductor device as recited in claim 15, further comprising: a gate contact in physical contact with the first gate structure at a location between the first transistor of the first transistor type and the first transistor of the second transistor type. 17. The semiconductor device as recited in claim 16, wherein the gate contact is formed to cover the width of the first gate structure without extending in the second direction substantially beyond either of the sidewall spacers of the first gate structure. 18. The semiconductor device as recited in claim 17, further comprising: a third gate structure positioned next to the second gate structure, the third gate structure having a substantially linear shape defined by a length and a width, the length of the third gate structure extending in the first direction and the width of the third gate structure extending in the second direction, the length of the third gate structure measured along a centerline of the third gate structure from a first end of the third gate structure to a second end of the third gate structure, the centerline of the third gate structure extending through a midpoint of the width of the third gate structure, the width of the third gate structure measured at a location halfway along the length of the third gate structure. 19. The semiconductor device as recited in claim 18, wherein the third gate structure includes a first portion that forms a gate electrode of a second transistor of the first transistor type, and wherein the gate structure includes a second portion that forms a gate electrode of a second transistor of the second transistor type, wherein the second transistor of the first transistor type shares a first shared active region with the first transistor of the first transistor type, and wherein the second transistor of the second transistor type shares a second shared active region with the second transistor of the first transistor type. 20. A method for manufacturing a semiconductor device, comprising: forming a first gate structure including a central conductive region and sidewall spacers disposed on side surfaces of the central conductive region, the first gate structure including a portion that forms a gate electrode of a transistor;forming a second gate structure including a central conductive region and sidewall spacers disposed on side surfaces of the central conductive region, the second gate structure including a portion positioned over a shallow trench isolation region and next to the portion of the first gate structure that forms the gate electrode of the transistor;forming an active area within a substrate between the central conductive region of the first gate structure and the shallow trench isolation region over which the second gate structure is positioned;forming an active area contact structure at a position between the first gate structure and the second gate structure, the active area contact structure formed to be in contact with the active area; andforming a photon absorption material between the first gate structure and the second gate structure and around the active area contact structure, the photon absorption material providing a minimal backscattering of photons incident upon a surface of the photon absorption material.
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