Systems and methods for long soft start time load switch control
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-003/08
F25D-017/02
F16K-031/06
출원번호
US-0871364
(2015-09-30)
등록번호
US-9822898
(2017-11-21)
발명자
/ 주소
Huang, Wen-Hung
Lin, Hsien Tsung
Wang, Chih-Kai
출원인 / 주소
Dell Products L.P.
대리인 / 주소
Jackson Walker L.L.P.
인용정보
피인용 횟수 :
0인용 특허 :
1
초록▼
A circuit may include a source input for receiving an input voltage, a load output for generating an output voltage, a load switch coupled at its source to the source input and coupled at its drain to the load output which is configured to pass the input voltage to the load output when the load swit
A circuit may include a source input for receiving an input voltage, a load output for generating an output voltage, a load switch coupled at its source to the source input and coupled at its drain to the load output which is configured to pass the input voltage to the load output when the load switch is activated, an enable input for receiving an enable voltage which is indicative of whether the load switch is to be activated or deactivated, and a leakage reduction circuit coupled between the enable input and a gate of the load switch, wherein the leakage reduction circuit is configured to electrically couple the gate of the load switch to the source of the load switch such that a source-to-gate voltage is maintained below a threshold voltage for activating the load switch when the enable voltage indicates that the load switch is to be deactivated.
대표청구항▼
1. A circuit comprising: a source input for receiving an input source voltage;a load output for generating an output voltage;a load switch coupled at its source terminal to the source input and coupled at its drain terminal to the load output, the load switch configured to pass the input source volt
1. A circuit comprising: a source input for receiving an input source voltage;a load output for generating an output voltage;a load switch coupled at its source terminal to the source input and coupled at its drain terminal to the load output, the load switch configured to pass the input source voltage to the load output when the load switch is activated;an enable input for receiving an enable voltage, the enable voltage indicative of whether the load switch is to be activated or deactivated; anda leakage reduction circuit coupled between the enable input and a gate terminal of the load switch, wherein the leakage reduction circuit is configured to electrically couple the gate terminal of the load switch to the source terminal of the load switch such that a source-to-gate voltage is maintained below a threshold voltage for activating the load switch when the enable voltage indicates that the load switch is to be deactivated, wherein the leakage reduction circuit comprises: an n-type field effect transistor coupled at its source terminal to a ground voltage and coupled at its gate terminal to the enable input such that a gate-to-source voltage of the n-type field effect transistor is approximately equal to the enable voltage;an n-p-n bipolar junction transistor coupled at its emitter terminal to the ground voltage and coupled at its base terminal to a drain terminal of the n-type field effect transistor; anda p-n-p bipolar junction transistor coupled at its emitter terminal to the source input, coupled at its base terminal to a collector terminal of the n-p-n bipolar junction transistor, and coupled at its collector terminal to the gate terminal of the load switch. 2. The circuit of claim 1, further comprising a capacitor coupled between the drain terminal of the load switch and gate terminal of the load switch. 3. The circuit of claim 2, wherein a capacitance of the capacitor is selected in order to provide for a soft start time of a valve coupled to the load output. 4. The circuit of claim 1, wherein the load switch comprises a p-type field effect transistor. 5. The circuit of claim 1, wherein the leakage reduction circuit is configured to electrically couple the gate terminal of the load switch to the source terminal of the load switch via a virtual short. 6. The circuit of claim 1, wherein the source-to-gate voltage is maintained at approximately zero volts. 7. The circuit of claim 1, wherein the base terminal of the p-n-p bipolar junction transistor is coupled to the collector terminal of the n-p-n bipolar junction transistor via a first resistor. 8. The circuit of claim 7, wherein the base terminal of the p-n-p bipolar junction transistor is coupled to the source terminal of the n-type field effect transistor via a second resistor. 9. The circuit of claim 1, wherein the gate terminal of the load switch is coupled to the source terminal of the load switch via a first resistor and the gate terminal of the load switch is coupled to the ground voltage via a second resistor. 10. A system comprising: a valve;a control circuit for controlling the valve, the control circuit comprising: a source input for receiving an input source voltage;a load output coupled to the valve for generating an output voltage for controlling the valve;a load switch coupled at its source terminal to the source input and coupled at its drain terminal to the load output, the load switch configured to pass the input source voltage to the load output when the load switch is activated;an enable input for receiving an enable voltage, the enable voltage indicative of whether the load switch is to be activated or deactivated; anda leakage reduction circuit coupled between the enable input and a gate terminal of the load switch, wherein the leakage reduction circuit is configured to electrically couple the gate terminal of the load switch to the source terminal of the load switch such that a source-to-gate voltage is maintained below a threshold voltage for activating the load switch when the enable voltage indicates that the load switch is to be deactivated, wherein the leakage reduction circuit comprises: an n-type field effect transistor coupled at its source terminal to a ground voltage and coupled at its gate terminal to the enable input such that a gate-to-source voltage of the n-type field effect transistor is approximately equal to the enable voltage;an n-p-n bipolar junction transistor coupled at its emitter terminal to the ground voltage and coupled at its base terminal to a drain terminal of the n-type field effect transistor; anda p-n-p bipolar junction transistor coupled at its emitter terminal to the source input, coupled at its base terminal to a collector terminal of the n-p-n bipolar junction transistor, and coupled at its collector terminal to the gate terminal of the load switch. 11. The system of claim 10, further comprising a capacitor coupled between the drain terminal of the load switch and gate terminal of the load switch. 12. The system of claim 11, wherein a capacitance of the capacitor is selected in order to provide for a soft start time of the valve. 13. The system of claim 10, wherein the load switch comprises a p-type field effect transistor. 14. The system of claim 10, wherein the leakage reduction circuit is configured to electrically couple the gate terminal of the load switch to the source terminal of the load switch via a virtual short. 15. The system of claim 10, wherein the source-to-gate voltage is maintained at approximately zero volts. 16. The system of claim 10, wherein the base terminal of the p-n-p bipolar junction transistor is coupled to the collector terminal of the n-p-n bipolar junction transistor via a first resistor. 17. The system of claim 16, wherein the base terminal of the p-n-p bipolar junction transistor is coupled to the source terminal of the n-type field effect transistor via a second resistor. 18. The system of claim 10, wherein the gate terminal of the load switch is coupled to the source terminal of the load switch via a first resistor and the gate terminal of the load switch is coupled to the ground voltage via a second resistor. 19. A method comprising, in a circuit comprising a source input for receiving an input source voltage, a load output for generating an output voltage, a load switch coupled at its source terminal to the source input and coupled at its drain terminal to the load output, the load switch configured to pass the input source voltage to the load output when the load switch is activated, and an enable input for receiving an enable voltage, the enable voltage indicative of whether the load switch is to be activated or deactivated, electrically coupling, with a leakage reduction circuit, the gate terminal of the load switch to the source terminal of the load switch such that a source-to-gate voltage is maintained below a threshold voltage for activating the load switch when the enable voltage indicates that the load switch is to be deactivated, wherein the leakage reduction circuit comprises: an n-type field effect transistor coupled at its source terminal to a ground voltage and coupled at its gate terminal to the enable input such that a gate-to-source voltage of the n-type field effect transistor is approximately equal to the enable voltage;an n-p-n bipolar junction transistor coupled at its emitter terminal to the ground voltage and coupled at its base terminal to a drain terminal of the n-type field effect transistor; anda p-n-p bipolar junction transistor coupled at its emitter terminal to the source input, coupled at its base terminal to a collector terminal of the n-p-n bipolar junction transistor, and coupled at its collector terminal to the gate terminal of the load switch.
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이 특허에 인용된 특허 (1)
Boyle William G. (Dallas TX) Goiffon John J. (Dallas TX) Pool Charles M. (Euless TX), Well control system.
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