Semiconductor device allowing metal layer routing formed directly under metal pad
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/52
H01L-023/528
H01L-027/088
H01L-023/485
H01L-023/522
H01L-023/00
출원번호
US-0356680
(2016-11-21)
등록번호
US-9824971
(2017-11-21)
발명자
/ 주소
Chen, Chun-Liang
출원인 / 주소
MEDIATEK INC.
대리인 / 주소
Hsu, Winston
인용정보
피인용 횟수 :
0인용 특허 :
9
초록▼
A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the se
A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.
대표청구항▼
1. A semiconductor device, comprising: a metal pad, positioned in a first metal layer of the semiconductor device;a first specific metal layer routing, formed in a second metal layer of the semiconductor device and under the metal pad; andat least one via plug for connecting the first specific metal
1. A semiconductor device, comprising: a metal pad, positioned in a first metal layer of the semiconductor device;a first specific metal layer routing, formed in a second metal layer of the semiconductor device and under the metal pad; andat least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, wherein the at least one via plug is formed directly under the metal pad, and comprises one or more via plugs. 2. The semiconductor device of claim 1, wherein the metal pad has a thickness smaller than 20 KA. 3. The semiconductor device of claim 1, wherein material of the metal pad is aluminum. 4. The semiconductor device of claim 1, wherein the first specific metal layer routing has a uniform pattern. 5. The semiconductor device of claim 4, wherein the uniform pattern has a metal density range between 30% and 70%. 6. The semiconductor device of claim 1, wherein the first specific metal layer routing comprises a plurality of sets of terminal lines corresponding to terminals of a plurality of field effect transistors (FETs), respectively. 7. The semiconductor device of claim 6, wherein there are oxide regions between the plurality of sets of terminal lines, and each oxide region has a width greater than 2 micrometers. 8. The semiconductor device of claim 6, wherein a set of terminal lines within the plurality of sets of terminal lines comprises a source terminal line and a drain terminal line respectively corresponding to a source terminal and a drain terminal of a FET within the plurality of FETs. 9. The semiconductor device of claim 8, wherein there is an oxide region between the source terminal line and the drain terminal line, and the oxide region has a width greater than 2 micrometers. 10. The semiconductor device of claim 1, further comprising: a second specific metal layer routing, formed on the second metal layer of the semiconductor device and connected to the first specific metal layer routing, wherein the second specific metal layer routing is not directly positioned under the metal pad. 11. The semiconductor device of claim 10, wherein the first specific metal layer routing comprises a plurality of sets of terminal lines corresponding to terminals of a plurality of field effect transistors (FETs), respectively; and the second specific metal layer routing comprises a plurality of sets of terminal lines corresponding to the plurality of sets of terminal lines of the first specific metal layer routing, respectively. 12. The semiconductor device of claim 11, wherein the plurality of sets of terminal lines of the second specific metal layer routing are extensions of the plurality of sets of terminal lines of the first specific metal layer routing, respectively. 13. The semiconductor device of claim 1, wherein the semiconductor device is a chip. 14. The semiconductor device of claim 1, wherein the first metal layer and the second metal layer are adjacent metal layers of the semiconductor device. 15. The semiconductor device of claim 1, wherein at least one size of at least one side of the at least one via plug is not less than 1 micrometer. 16. The semiconductor device of claim 15, wherein a size of a first side of the at least one via plug is not less than 1 micrometer, and a size of a second side of the at least one via plug is not less than 3 micrometers. 17. The semiconductor device of claim 1, wherein the at least one via plug comprises multiple via plugs, directly under the metal pad. 18. A semiconductor device, comprising: a metal pad, positioned in a first metal layer of the semiconductor device;a first specific metal layer routing and a second specific metal layer routing, formed in a second metal layer of the semiconductor device; andat least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad. 19. The semiconductor device of claim 18, wherein the via plug is formed directly under the metal pad.
Knight Thomas F. (Belmont MA) Salzman David B. (Washington DC), Apparatus for non-conductively interconnecting integrated circuits using half capacitors.
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