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In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit i

In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor. The series resistor is coupled to the gate terminal.

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1. Apparatus, comprising: a transistor having: a source and a drain coupled between an input voltage terminal and an output voltage terminal; and a gate terminal;a charge pump having: an output node coupled to the gate terminal; and a clock input;an oscillator coupled to generate a clock signal;a cl

1. Apparatus, comprising: a transistor having: a source and a drain coupled between an input voltage terminal and an output voltage terminal; and a gate terminal;a charge pump having: an output node coupled to the gate terminal; and a clock input;an oscillator coupled to generate a clock signal;a clock enable circuit coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal; anda comparator coupled to output the enable signal to the clock enable circuit in response to: a comparison between a reference current and a current through a series resistor; and a voltage at the gate terminal being lower than a predetermined gate voltage level; wherein the series resistor is coupled to the gate terminal. 2. The apparatus of claim 1, wherein the comparator is a Schmitt trigger. 3. The apparatus of claim 2, wherein a voltage at an input node of the comparator falls in response to the current through the series resistor being lower than the reference current. 4. The apparatus of claim 3, wherein the Schmitt trigger is coupled to output a high signal in response to a voltage at the input node falling below a threshold voltage. 5. The apparatus of claim 3, wherein the Schmitt trigger is coupled to output a low signal in response to a voltage at the input node rising above a threshold voltage. 6. The apparatus of claim 1, wherein the charge pump is coupled to increase a voltage at the gate terminal, responsive to receiving clock pulses at the clock input. 7. The apparatus of claim 1, wherein a voltage at the gate terminal is adjustable by adjusting at least one of the reference current and the series resistor. 8. The apparatus of claim 1, wherein a voltage output by the charge pump at the gate terminal is regulatable to a predetermined voltage level. 9. Apparatus, comprising: a transistor having: a source and a drain coupled between an input voltage terminal and an output voltage terminal; and a gate terminal;a charge pump having: an output node coupled to the gate terminal; and a clock input;an oscillator coupled to generate a clock signal;a clock enable circuit coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal;a comparator coupled to output the enable signal to the clock enable circuit in response to a comparison between a reference current and a current through a series resistor; wherein the series resistor is coupled to the gate terminal;a reference current source coupled to generate the reference current; anda current mirror coupled to mirror the reference current, and having an output node coupled to an input node of the comparator. 10. Apparatus, comprising: a first transistor having: a source and a drain coupled between an input voltage terminal and an output voltage terminal; and a gate terminal;a charge pump having: an output node coupled to the gate terminal; and a clock input;an oscillator coupled to generate a clock signal;a clock enable circuit coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal;a comparator coupled to output the enable signal to the clock enable circuit in response to a comparison between a reference current and a current through a series resistor; wherein the series resistor is coupled to the gate terminal;a second transistor having a source terminal coupled to the input voltage terminal and a gate coupled to a common gate terminal; anda third transistor having a gate coupled to the common gate terminal and having a source terminal coupled to one terminal of the series resistor;wherein the second and third transistors are coupled to make the current through the series resistor proportional to a difference between a voltage at the gate terminal and a voltage at the input voltage terminal, divided by a resistance of the series resistor. 11. A gate driver integrated circuit for providing a gate voltage to a power FET having a current conduction path coupled between an input terminal and an output terminal, comprising: a charge pump having: a clock input; and an output node coupled to a gate voltage output terminal;a clock enable circuit coupled to: receive clock pulses from an oscillator; and selectively output the clock pulses to the clock input, responsive to a clock enable signal;a comparator coupled to: compare a voltage at a summing node to a threshold; and output the clock enable signal in response to the comparison;a series resistor coupled between the gate voltage output terminal and the summing node; anda reference current source coupled to the summing node. 12. The gate driver integrated circuit of claim 11, wherein the comparator is coupled to output a high voltage on the clock enable signal in response to the voltage at the summing node falling below a first threshold. 13. The gate driver integrated circuit of claim 11, wherein the comparator is configured to output a low voltage on the clock enable signal in response to the voltage at the summing node rising above a second threshold. 14. The gate driver integrated circuit of claim 11, wherein the comparator is a Schmitt trigger. 15. The gate driver integrated circuit of claim 11, comprising: a first transistor having a source terminal coupled to the input terminal and having a first gate at a common gate terminal;a second transistor having a second gate at the common gate terminal and having a source terminal at a first terminal of the series resistor; andthe series resistor having a second terminal coupled to the gate voltage output terminal;wherein the first and second transistors are coupled to make a current through the series resistor proportional to a difference between a voltage at the gate voltage output terminal and a supply voltage at the input terminal, divided by a resistance of the series resistor. 16. The gate driver integrated circuit of claim 11, comprising: a current mirror coupled to receive a reference current from the reference current source and coupled to supply the reference current to the summing node, so that a current at the summing node is proportional to a difference between a current through the series resistor and the reference current. 17. The gate driver integrated circuit of claim 16, wherein the gate driver integrated circuit is coupled to output a voltage at the gate voltage output terminal that is directly proportional to a resistance of the series resistor and to the reference current. 18. A method for controlling a gate voltage to a driver transistor having a conduction path coupled between an input voltage and an output terminal, comprising: supplying a gate voltage from a charge pump to a gate terminal of a driver transistor, responsive to an enable signal;monitoring the gate voltage by coupling a series resistor between the gate voltage and an input voltage, and coupling a current through the series resistor to a summing node;coupling a reference current to the summing node;comparing a voltage at the summing node to a first threshold, and outputting a high voltage on the enable signal in response to the voltage being less than the first threshold; andcomparing the voltage at the summing node to a second threshold, and outputting a low voltage on the enable signal in response to the voltage being greater than a second threshold. 19. The method of claim 18, comprising: adjusting the voltage at the gate terminal by adjusting at least one of a resistance of the series resistor and the reference current.