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Semiconductor device wtih an interconnecting semiconductor electrode between first and second semiconductor electrodes and method of manufacture therefor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/78
  • H01L-029/66
  • H01L-027/07
  • H01L-021/8234
  • H01L-029/423
  • H01L-027/088
출원번호 US-0707150 (2015-05-08)
등록번호 US-9837526 (2017-12-05)
우선권정보 WO-PCT/IB2014/002946 (2014-12-08)
발명자 / 주소
  • Dupuy, Philippe
  • Grandry, Hubert
출원인 / 주소
  • NXP USA, Inc.
대리인 / 주소
    Jacobsen, Charlene R.
인용정보 피인용 횟수 : 2  인용 특허 : 48

초록

A semiconductor product comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode; a first switch, between the first semiconductor electrode and the third semiconductor electrode, provided by

대표청구항

1. A semiconductor product, comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode;a first switch, between the first semiconductor electrode and the third semiconductor electrode, provided

이 특허에 인용된 특허 (48)

  1. Anderson, Samuel J.; Okada, David N., Bi-directional MOSFET power switch with single metal layer.
  2. Robb,Stephen P.; Robb,Francine Y.; Hightower,Robert F., Bi-directional transistor and method therefor.
  3. Robb, Francine Y.; Robb, Stephen P., Bi-directional transistor with by-pass path and method therefor.
  4. Robb, Francine Y.; Robb, Stephen P., Bi-directional transistor with by-pass path and method therefor.
  5. Robb, Francine Y.; Robb, Stephen P., Bi-directional transistor with by-pass path and method therefor.
  6. Grugett Bruce C., Biasing circuit for reducing body effect in a bi-directional field effect transistor.
  7. Williams Richard K. (Cupertino CA) Jew Kevin (Fremont CA) Chen Jun W. (Saratoga CA), Bidirectional blocking lateral MOSFET with improved on-resistance.
  8. Williams Richard K. (Cupertino CA), Bidirectional current blocking MOSFET for battery disconnect switching including protection against reverse connected ba.
  9. Stefanov, Evgueniy; De Fresart, Edouard Denis; Zitouni, Moaniss, Bidirectional power transistor with shallow body trench.
  10. Williams Richard K., Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench.
  11. Chen, Po-Yu, Dual gate lateral MOSFET.
  12. Warren Keith O., Electrostatically force balanced silicon accelerometer.
  13. Youssef, Michael; Mirzaei, Ahmad; Darabi, Hooman, Feedback-based linearization of voltage controlled oscillator.
  14. Tihanyi Jenoe,DEX, Field-effect-controllable, vertical semiconductor component and method for producing the same.
  15. Haeusler, Alfred, Fully embedded micromechanical device, system on chip and method for manufacturing the same.
  16. Li, Jian; Owyang, King, High current density power field effect transistor.
  17. Stultz, Julie Lynn; Daigle, Tyler, High-voltage bulk driver using bypass circuit.
  18. Huang, Shao-Chang; Lin, Wei-Yao; Lee, Tang-Lung; Chang, Kun-Wei; Chen, Lin-Fwu; Lee, Wen-Hao; Yen, Luan-Yi; Chang, Yu-Chun, High-voltage selecting circuit which can generate an output voltage without a voltage drop.
  19. Ishikawa,Hiroshi; Nakamura,Yoshitaka; Tokunaga,Hiroshi; Nagata,Kenji, Inertial sensor.
  20. Deng, Shengling; Hossain, Zia, Insulated gate semiconductor device having a shield electrode structure.
  21. Hossain, Zia, Insulated gate semiconductor device having shield electrode structure.
  22. Grose,William E.; Legat,Timothy J.; Patel,Sanmukh M., Integrated reverse battery protection circuit for an external MOSFET switch.
  23. Hazelton Lawrence Dean ; Strayer Lance Ronald, Low loss reverse battery protection.
  24. Sreekantham, Sreevatsa; Ho, Ihsiu; Session, Fred; Naylor, Kent, Low resistance gate for power MOSFET applications and method of manufacture.
  25. Schlarmann, Mark E.; Lin, Yizhen, MEMS device assembly and method of packaging same.
  26. Meiser, Andreas; Zundel, Markus, Method for producing a semiconductor component.
  27. Grivna,Gordon M.; Robb,Francine Y., Method of forming an MOS transistor and structure therefor.
  28. Dawson, Chad S.; Li, Fengyuan; Montez, Ruben B.; Stevens, Colin B., Method of making a MEMS die having a MEMS device on a suspended structure.
  29. Burke, Peter A.; Ameele, Eric J., Method of making an insulated gate semiconductor device and structure.
  30. Potter,Michael D., Micro-electro-mechanical switch and a method of using and making thereof.
  31. Dhuler Vijayakumar R. ; Koester David A. ; Walters Mark D. ; Markus Karen W., Microelectromechanical devices including rotating plates and related methods.
  32. William A. Clark ; Mark A. Lemkin ; Thor N. Juneau ; Allen W. Roessig, Microfabricated structures with trench-isolation using bonded-substrates and cavities.
  33. Suzuki Yoshihiko,JPX ; Hara Shinya,JPX, Micromechanical sensor for scanning thermal imaging microscope and method of making the same.
  34. Neukermans Armand P. (3510 Arbutus Ave. Palo Alto CA 94303) Slater Timothy G. (San Francisco CA), Monolithic silicon rate-gyro with integrated sensors.
  35. Kuo,Chang Fu; Tseng,Po Sen; Wang,Shou Tsung; Ko,Ling Wei, Phase-locked loop with VCO tuning sensitivity compensation.
  36. He, Qing, Power supply reverse bias protection circuit for protecting both analog and digital devices coupled thereto.
  37. Schulze, Hans-Joachim; Mauder, Anton; Strack, Helmut; Hirler, Franz, Power transistor device vertical integration.
  38. Wu, Yujing; Pearse, Jeffrey, Semiconductor bidirectional switching device.
  39. Wu, Yujing; Pearse, Jeffrey, Semiconductor bidirectional switching device and method.
  40. Nakata, Kazunari; Narazaki, Atsushi; Honda, Shigeto; Motonami, Kaoru, Semiconductor device.
  41. Grebs,Thomas E.; Dolny,Gary M., Semiconductor power device having a top-side drain using a sinker trench.
  42. Mizuno Koki,JPX ; Okada Hiroshi,JPX ; Toyoda Inao,JPX ; Kanosue Masakazu,JPX ; Suzuki Yasutoshi,JPX ; Yokoyama Kenichi,JPX, Semiconductor sensor with a built-in amplification circuit.
  43. Bhalla, Anup; Lui, Sik K., Shielded gate trench (SGT) MOSFET devices and manufacturing processes.
  44. Dawson, Chad S.; Hooper, Stephen R., Stress isolation for MEMS device.
  45. Combi, Chantal; Vigna, Benedetto; Ziglioli, Federico Giovanni; Baldo, Lorenzo; Magugliani, Manuela; Lasalandra, Ernesto; Riva, Caterina, Substrate-level assembly for an integrated device, manufacturing process thereof and related integrated device.
  46. Stafanov, Evgueniy; De Fresart, Edouard Denis; Grandry, Hubert Michel, Transistor body control circuit and an integrated circuit.
  47. Hsieh, Fu-Yuan, Trench MOSFET having a top side drain.
  48. Williams Richard K. ; Grabowski Wayne ; Darwish Mohamed ; Korec Jacek, Trench-gated MOSFET with bidirectional voltage clamping.

이 특허를 인용한 특허 (2)

  1. Perruchoud, Philippe; Grandry, Hubert; Guillot, Laurent, Half-bridge circuit, H-bridge circuit and electronic system.
  2. Qin, Ganming; Khemka, Vishnu; Radic, Ljubo; Grote, Bernhard; Saxena, Tanuj; Zitouni, Moaniss, Termination design for trench superjunction power MOSFET.
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