Optimized flash memory device for miniaturized devices
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
A61N-001/37
A61N-001/372
A61N-001/36
G06F-009/445
출원번호
US-0262742
(2016-09-12)
등록번호
US-9861826
(2018-01-09)
발명자
/ 주소
Gordon, Charles R
Bigelow, Duane R
출원인 / 주소
Medtronic, Inc.
인용정보
피인용 횟수 :
0인용 특허 :
17
초록▼
An implantable medical device have an associated memory device is disclosed. The implantable medical device utilizes techniques for optimizing one or more embedded operations of the memory device, such operations including programming, reading or erasing data. The techniques for optimizing the embed
An implantable medical device have an associated memory device is disclosed. The implantable medical device utilizes techniques for optimizing one or more embedded operations of the memory device, such operations including programming, reading or erasing data. The techniques for optimizing the embedded operations include controlling the operations as a function of an energy source of the implantable medical device.
대표청구항▼
1. A method of programming a memory device of an implantable medical device, comprising: computing, by one or more processors of the implantable medical device, a parameter of a battery of the implantable medical device;erasing, by the one or more processors, a memory sector of the memory device;det
1. A method of programming a memory device of an implantable medical device, comprising: computing, by one or more processors of the implantable medical device, a parameter of a battery of the implantable medical device;erasing, by the one or more processors, a memory sector of the memory device;determining, by the one or more processors, a programming delay based on a function of the computed parameter of the battery;performing, by the one or more processors, an iterative programming of a plurality of elements in the memory sector; andapplying, by the one or more processors, the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements. 2. The method of claim 1, wherein a value of the programming delay is defined as a function of the parameter of the battery. 3. The method of claim 1, wherein the computed parameter is a remaining amount of energy stored by the battery. 4. The method of claim 1, wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector. 5. The method of claim 1, further comprising receiving a memory address designator indicating the memory sector to be programmed. 6. The method of claim 1, wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases. 7. One or more processors of an implantable medical device configured to: compute a parameter of a battery of the implantable medical device;erase a memory sector of the memory device;determine a programming delay based on a function of the computed parameter of the battery;perform an iterative programming of a plurality of elements in the memory sector; andapply the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements. 8. The one or more processors of claim 7, wherein a value of the programming delay is defined as a function of the parameter of the battery. 9. The one or more processors of claim 7, wherein the computed parameter is a remaining amount of energy stored by the battery. 10. The one or more processors of claim 7, wherein the one or more processors are further configured to receive a memory address designator indicating the memory sector to be programmed. 11. The one or more processors of claim 7, wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases. 12. The one or more processors of claim 7, wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector. 13. A non-transitory computer-readable medium comprising instructions that, when executed, cause one or more processors of an implantable medical device to: compute a parameter of a battery of the implantable medical device;erase a memory sector of the memory device;determine a programming delay based on a function of the computed parameter of the battery;perform an iterative programming of a plurality of elements in the memory sector; andapply the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements. 14. The computer-readable medium of claim 13, wherein a value of the programming delay is defined as a function of the parameter of the battery. 15. The computer-readable medium of claim 13, wherein the computed parameter is a remaining amount of energy stored by the battery. 16. The computer-readable medium of claim 13, wherein the instructions further cause the one or more processors to receive a memory address designator indicating the memory sector to be programmed. 17. The computer-readable medium of claim 13, wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases. 18. The computer-readable medium of claim 13, wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector.
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이 특허에 인용된 특허 (17)
Shelton, Douglas Edward; MacPeak, John Howard; Breashears, Eddie Hearl; Pickelsimer, Bruce Lynn, Adaptive programming for flash memories.
Haeberli Andreas M. ; Werner Carl W. ; Wang Cheng-Yuan Michael ; So Hock C. ; Wong Leon Sea Jiunn ; Wong Sau C., Adjustable level shifter circuits for analog or multilevel memories.
Mills Duane R. ; Dipert Brian Lyn ; Sambandan Sachidanandan ; McCormick Bruce ; Pashley Richard D., Flash memory including a mode register for indicating synchronous or asynchronous mode of operation.
Dallabora Marco,ITX ; Villa Corrado,ITX ; Bartoli Simone,ITX ; Defendi Marco,ITX, Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device.
Klein George J.,CAX ; Warkentin Dwight H. ; Riff Kenneth M. ; Lee Brian B. ; Carney James K. ; Turi Gregg ; Varrichio Anthony J., Minimally invasive implantable device for monitoring physiologic events.
Kanai, Tatsunori; Yamada, Yutaka; Yoshida, Hideki; Tarui, Masaya, Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand.
Wyborny Paul B. (Fridley MN) Roline Glenn M. (Anoka MN) Nichols Lucy M. (Maple Grove MN) Thompson David L. (Fridley MN), Telemetry format for implanted medical device.
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