초록 ▼

The present disclosure includes circuits and methods for controlling the operation of a switching regulator. Closing and opening high side and low side switches may be controlled so that an inductor current may be used to charge and/or discharge an intermediate switching node when both switches are

The present disclosure includes circuits and methods for controlling the operation of a switching regulator. Closing and opening high side and low side switches may be controlled so that an inductor current may be used to charge and/or discharge an intermediate switching node when both switches are open. In one embodiment, delays between a low-to-high transition and a high-to-low transition of an AC stage may be cycled over multiple periods of a DC stage.

대표청구항 ▼

1. A method, comprising: turning off a first switch in a first stage of a switching regulator, the switching regulator further comprising a second stage in parallel with the first stage, wherein each of the first and second stages of the switching regulator comprises a buck configuration regulator s

1. A method, comprising: turning off a first switch in a first stage of a switching regulator, the switching regulator further comprising a second stage in parallel with the first stage, wherein each of the first and second stages of the switching regulator comprises a buck configuration regulator stage;turning on a second switch in the first stage of the switching regulator after the first switch is turned off,wherein the second switch is turned on after one of a plurality of controlled time periods, wherein a current in an inductor changes a voltage on a node between a first terminal of the first switch and a first terminal of the second switch, and wherein the controlled time periods are configured according to different output currents so that the voltage on the node between the first switch and the second switch is equal to a voltage on a second terminal of the second switch after each controlled time period when the second switch is turned on. 2. The method of claim 1, wherein in a first mode of operation the first stage cancels ripple in the second stage, and wherein the plurality of controlled time periods occur over a period of the second stage, wherein different controlled time periods correspond to different inductor currents in the first stage during a plurality of transitions. 3. The method of claim 1, wherein a first plurality of controlled time periods correspond to different inductor currents in the first stage during a first plurality of high to low transitions of a switching node in the first stage, and wherein a second plurality of controlled time periods correspond to different inductor currents in the first stage during a second plurality of low to high transitions of the switching node in the first stage. 4. The method of claim 3, wherein the first plurality of controlled time periods are configured during low to high transitions, and wherein the second plurality of controlled time periods are configured during high to low transitions. 5. The method of claim 1, wherein the plurality of controlled time periods repeat over a plurality of periods of the second stage. 6. The method of claim 1, wherein the plurality of controlled time periods are stored as a plurality of digital values. 7. The method of claim 1, wherein the first switch and the second switch are MOS transistors. 8. The method of claim 1, wherein the first switch is a high side switch and the second switch is a low side switch, and wherein the current in the inductor reduces the voltage on the node. 9. The method of claim 1, wherein the first switch is a low side switch and the second switch is a high side switch, and wherein the current in the inductor increases the voltage on the node. 10. A switching regulator circuit, comprising: a first stage and a second stage in parallel, wherein each of the first and second stages of the switching regulator comprises a buck configuration regulator stage, the first stage comprising:a first switch having a first terminal coupled to a first voltage and a second terminal coupled to a switching node;a second switch having a first terminal coupled to the switching node and a second terminal coupled to a second voltage;an inductor having a first terminal coupled to the switching node and a second terminal coupled to a switching regulator output node; anddrive circuitry to produce a first signal to turn the first switch on and off and to produce a second signal to turn the second switch on and off,wherein the second switch is turned on after first switch is turned off, wherein a time period between the first switch turning off and the second switch turning on is one of a plurality of controlled time periods, wherein a current in the inductor changes a voltage on the switching node, and wherein the controlled time periods are configured according to different output currents so that the voltage on the switching node is equal to a voltage on the second terminal of the second switch after the controlled time period when the second switch is turned on. 11. The switching regulator circuit of claim 10, further comprising a programmable delay circuit to produce the controlled time period. 12. The switching regulator circuit of claim 10, wherein in a first mode of operation the first stage cancels ripple in the second stage, and wherein different controlled time periods correspond to different inductor currents in the first stage during a plurality of transitions. 13. The switching regulator circuit of claim 10, wherein a first plurality of controlled time periods correspond to different inductor currents in the first stage during a first plurality of high to low transitions of the switching node in the first stage, and wherein a second plurality of controlled time periods correspond to different inductor currents in the first stage during a second plurality of low to high transitions of the switching node in the first stage. 14. The switching regulator circuit of claim 13, wherein the first plurality of controlled time periods are configured during low to high transitions, and wherein the second plurality of controlled time periods are configured during high to low transitions. 15. The switching regulator circuit of claim 10, wherein the plurality of controlled time periods repeat over a plurality of periods of the second stage. 16. The switching regulator circuit of claim 10, wherein the plurality of controlled time periods are stored as a plurality of digital values. 17. The switching regulator circuit of claim 10, wherein the first switch and the second switch are MOS transistors. 18. The switching regulator circuit of claim 10, wherein the first switch is a high side switch and the second switch is a low side switch, and wherein the current in the inductor reduces the voltage on the node. 19. The switching regulator circuit of claim 10, wherein the first switch is a low side switch and the second switch is a high side switch, and wherein the current in the inductor increases the voltage on the node.