최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0582363 (2014-12-24) |
등록번호 | US-9869701 (2018-01-16) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 566 |
A system for generation of electrical power including an inverter connected to a photovoltaic source including a theft prevention and detection feature. A first memory is permanently attached to the photovoltaic source. The first memory is configured to store a first code. A second memory is attache
A system for generation of electrical power including an inverter connected to a photovoltaic source including a theft prevention and detection feature. A first memory is permanently attached to the photovoltaic source. The first memory is configured to store a first code. A second memory is attached to the inverter. The second memory configured to store a second code. During manufacture or installation of the system, the first code is stored in the first memory attached to the photovoltaic source. The second code based on the first code is stored in the second memory. Prior to operation of the inverter, the first code is compared to the second code and based on the comparison; the generation of the electrical power is enabled or disabled.
1. A method, comprising: receiving a first impedance value associated with at least one direct current (DC) power source and measured based on a first signal applied to a DC power line of the at least one DC power source;storing the first impedance value;receiving a second impedance value associated
1. A method, comprising: receiving a first impedance value associated with at least one direct current (DC) power source and measured based on a first signal applied to a DC power line of the at least one DC power source;storing the first impedance value;receiving a second impedance value associated with the at least one DC power source and measured based on a second signal applied to the DC power line of the at least one DC power source;comparing the stored first impedance value to the second impedance value; anddetermining whether to transmit an alert based on the comparing. 2. The method of claim 1, wherein the first signal and the second signal each comprises an alternating current. 3. The method of claim 1, wherein the determining whether to transmit an alert comprises: determining whether a difference between the stored first impedance value and the second impedance value is greater than a predefined threshold; andin response to determining that the difference is greater than the predefined threshold, transmitting the alert. 4. The method of claim 1, further comprising: determining whether a third impedance value is received in an expected time after receiving the second impedance value; andin response to failing to receive the third impedance value in the expected time, transmitting an alert. 5. The method of claim 1, further comprising: periodically receiving an impedance value associated with the at least one DC power source; andcomparing the periodically received impedance value to a previously stored impedance value. 6. The method of claim 1, wherein the receiving the first impedance value associated with at least one DC power source comprises: receiving, from an impedance probe, the first impedance value associated with at least one DC power source and measured based on the first signal. 7. The method of claim 1, further comprising: applying, to the DC power line, the second signal comprising an alternating current during the at least one DC power source transfers DC power to an inverter coupled to the DC power line. 8. An apparatus, comprising: a memory; anda processor configured to: receive a first impedance value associated with at least one direct current (DC) power source and measured based on a first signal applied to a DC power line of the at least one DC power source;store the first impedance value in the memory;receive a second impedance value associated with the at least one DC power source based on a second signal applied to the DC power line of the at least one DC power source;compare the stored first impedance value to the second impedance value; anddetermine whether to transmit an alert based on the comparison. 9. The apparatus of claim 8, wherein the first signal and the second signal each comprises an alternating current. 10. The apparatus of claim 8, wherein the processor being configured to determine whether to transmit an alert comprises: the processor being configured to: determine whether a difference between the stored first impedance value and the second impedance value is greater than a predefined threshold; andin response to determining that the difference is greater than the predefined threshold, transmit the alert. 11. The apparatus of claim 8, wherein the processor is further configured to: determine whether a third impedance value is received in an expected time after receiving the second impedance value; andin response to failing to receive the third impedance value in the expected time, transmit an alert. 12. The apparatus of claim 8, wherein the processor is further configured to: periodically receive an impedance value associated with the at least one DC power source; andcompare the periodically received impedance value to a previously stored impedance value. 13. The apparatus of claim 8, wherein the processor being configured to receive the first impedance value associated with at least one DC power source comprises: the processor being configured to receive, from an impedance probe, the first impedance value associated with at least one DC power source and measured based on the first signal. 14. The apparatus of claim 8, wherein the processor is configured to apply the second signal comprising an alternating current during the at least one DC power source transfers DC power to an inverter coupled to the DC power line. 15. A system, comprising: a plurality of direct current (DC) power sources connected in series; anda processor configured to: receive a first impedance value associated with the plurality of DC power sources and measured based on a first signal applied to a DC power line coupled to at least one of the plurality of DC power sources;store the first impedance value;receive a second impedance value associated with the plurality of DC power sources and measured based on a second signal applied to the DC power line;compare the stored first impedance value to the second impedance value; anddetermine whether to transmit an alert based on the comparison. 16. The system of claim 15, wherein the first signal and the second signal each comprises an alternating current. 17. The system of claim 15, wherein the processor being configured to determine whether to transmit an alert comprises: the processor being configured to determine whether a difference between the stored first impedance value and the second impedance value is greater than a predefined threshold. 18. The system of claim 17, wherein the processor is further configured to: in response to determining that the difference is greater than the predefined threshold, transmit the alert. 19. The system of claim 15, wherein the processor is further configured to: determine whether a third impedance value is received in an expected time after receiving the second impedance value; andin response to failing to receive the third impedance value in the expected time, transmit an alert. 20. The system of claim 15, wherein the processor is further configured to: periodically receive an impedance value associated with the plurality of DC power sources; andcompare the periodically received impedance value to a previously stored impedance value.
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