[특허]High speed controllable load

High speed controllable load 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-031/02 G01R-031/327
출원번호	US-0383233 (2016-12-19)
등록번호	US-9869719 (2018-01-16)
발명자 / 주소	Brazis, Jr., Paul W.
출원인 / 주소	UL LLC
대리인 / 주소	Marshall, Gerstein & Borun LLP
인용정보	피인용 횟수 : 0 인용 특허 : 202

초록 ▼

A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.

대표청구항 ▼

1. A method of testing an arc fault circuit interrupter (AFCI) comprising: storing a waveform representative of an arc fault;coupling the AFCI and a controllable load in series with a power source;retrieving the stored waveform;sensing a current through the controllable load and the AFCI;adjusting a resistance in the controllable load based on the sensed current such that the current through the controllable load and the AFCI replicates the stored waveform at the AFCI. 2. The method of claim 1, wherein storing the waveform comprises: storing a plurality of waveforms representative of a corresponding plurality of arc faults. 3. The method of claim 2, further comprising: storing an output waveform of one of a voltage or current measured at the AFCI. 4. The method of claim 1, further comprising: determining whether the AFCI correctly responds to the current drawn through the controllable load. 5. A tester for an arc fault circuit interrupter (AFCI) comprising: a power source with a supply connection adapted to be coupled to a first AFCI connection of an AFCI and a return connection adapted to be coupled to a second AFCI connection of an AFCI;a controllable load with a first connection, a second connection, and a control connection, the first connection coupled to the second AFCI connection and the second connection coupled to the return connection of the power source;a waveform generator that reproduces waveforms indicative of an arc fault;a current sensor that senses current through the AFCI and the controllable load; anda control stage coupled to the waveform generator and to the control connection of the controllable load, wherein the control stage causes a resistance of the controllable load to change in response to (i) an output of the waveform generator, and (ii) the sensed current, such that a waveform generated by the waveform generator is replicated at the AFCI. 6. The tester of claim 5, further comprising: a voltage sensor to verify a phase angle between current and voltage at the AFCI. 7. The tester of claim 6, further comprising: a zero crossing detector to capture a zero crossing and polarity of a voltage of the power source. 8. The tester of claim 5, wherein the control stage comprises: an optical isolation stage that allows separation of an electrical ground of the power source from an electrical ground of the waveform generator. 9. The tester of claim 5, wherein the controllable load comprises: a high power resistor in series with at least one power field effect transistor (FET). 10. The tester of claim 9, wherein the at least one power FET comprises an array of N-channel power FETs. 11. The tester of claim 10, wherein the at least one power FET has a current rating of 100 amperes. 12. The tester of claim 5, wherein the control stage has an analog bandwidth of about 0.7 Hz to about 200 MHz. 13. The tester of claim 5, further comprising: a waveform library storing a plurality of waveforms indicative of a plurality of corresponding arc faults, and wherein the waveform generator reproduces waveforms indicative of the stored waveforms. 14. The tester of claim 13, wherein each stored waveform is stored as a streaming waveform file. 15. A method of testing an arc fault circuit interrupter (AFCI) comprising: providing a waveform library with a plurality of stored waveforms, each of the plurality of stored waveforms representing a test condition for the AFCI;providing a waveform generator in communication with the waveform library for generating one of the plurality of stored waveforms for performance testing of the AFCI;providing a control stage coupled to the waveform generator, the control stage for outputting a control signal;providing a controllable load that varies its resistance responsive to the control signal;coupling an AFCI in series with the controllable load and a power source;accepting the one of the plurality of stored waveforms at the control stage;sensing a current through the controllable load and the AFCI;creating the control signal at the control stage based on the one of the plurality of stored waveforms and the sensed currentadjusting a current through the controllable load and the AFCI proportionally to the control signal such that the current through the controllable load and the AFCI replicates the one of the plurality of stored waveforms; anddetermining how the AFCI responds to a current through the controllable load and the AFCI as the resistance is adjusted. 16. The method of claim 15, further comprising: passing the control signal through an optical isolation stage that separates a ground of the control stage and a ground of the controllable load. 17. The method of claim 15, wherein providing the controllable load comprises: providing a controllable load with a current rating of at least 100 amperes and a response time for changing between two current levels of at most 1 microsecond. 18. The method of claim 15, further comprising: determining that the AFCI interrupts current having an arc profile and passes current having a nuisance load profile. 19. The method of claim 1, further comprising: generating a difference signal corresponding to a difference between (i) the retrieved waveform and (ii) an observed waveform generated using the sensed current,wherein adjusting the resistance in the controllable load includes adjusting the resistance using the difference signal. 20. The tester of claim 5, wherein the control stage comprises a circuit configured to generate a difference signal voltage corresponding to a difference between (i) a first voltage indicative of the sensed current, and (ii) a second voltage indicative of the waveform generated by the waveform generator.

이 특허에 인용된 특허 (202)

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Mackenzie Raymond Warren, Plug-in multifunction tester for AC electrical distribution system.
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Elms, Robert T.; Foley, Brendan A.; Parker, Kevin L., Power circuit tester apparatus and method.
상세보기
Rockwell, Daniel J.; Steiner, James P., Power line fault detector and analyzer.
상세보기
John E. Stroth ; Peter Stroth ; Joachim Wottrich DE, Power line testing device with signal generator and signal detector.
상세보기
Moriguchi Haruo,JPX ; Danjo Kenzo,JPX ; Hashimoto Takashi,JPX, Power supply apparatus for plasma arc utilizing equipment.
상세보기
Morris, Robert Allan, Pre-emptive circuit breaker with arc fault and fault lockout short circuit protection.
상세보기
Gubisch Andrew D. (Arlington MA) West James L. (Concord MA) Miljanic Petar (Belgrade YUX) Lualdi ; Jr. Paul L. (Wellesley MA), Precision voltage/current/power source.
상세보기
Radosavljevic, Dejan; Savicki, Jr., Gerald R.; Weeks, Richard, Protection device with a contact breaker mechanism.
상세보기
Radosavljevic,Dejan; Packard,Thomas N.; Macbeth,Bruce F., Protection device with lockout test.
상세보기
Finlay, Sr.,David A.; Morgan,Kent; Murphy,Patrick J.; Radosavljevic,Dejan; Richards,Jeffrey C.; Savicki, Jr.,Gerald R.; Weeks,Richard; Wilson,Gary, Protection device with power to receptacle cut-off.
상세보기
Franklin Frederick F. (3501 Tiffany Ridge Cincinnati OH 45241), Protective circuits and devices for the prevention of fires.
상세보기
Radosavljevic, Dejan; Packard, Thomas, Protective device with end of life indicator.
상세보기
Finlay, Sr., David A.; Packard, Thomas N.; Macbeth, Bruce F., Protective device with end-of-life indication before power denial.
상세보기
Morgan,Kent; Weeks,Richard; Murphy,Patrick J.; Savicki, Jr.,Gerald R.; Finlay, Sr.,David A., Protective device with miswire protection.
상세보기
Packard,Thomas N.; Malley,Daniel P.; Finlay, Sr.,David A., Protective device with miswire protection.
상세보기
Radosavljevic,Dejan; Weeks,Richard, Protective device with tamper resistant shutters.
상세보기
Huang,Huadao; Li,Chengli, Receptacle device having circuit interrupting and reverse wiring protection.
상세보기
Huang,Huadao; Lu,Huayang, Receptacle device having protection against arc faults and leakage currents.
상세보기
MacKenzie Raymond W. (Baldwin Borough PA) Wafer John A. (Brighton Township PA), Self testing circuit breaker ground fault and sputtering arc trip unit.
상세보기
Baldwin,John R.; Bonilla,Nelson; DeBartolo, Jr.,Joseph; Lutz,David; Mortun,Sorin I.; Yu,Daming, Self testing digital fault interrupter.
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Behzad Rezvani, Sensor analyzer with reduced low frequency noise.
상세보기
Rivers, Jr.,Cecil; Adeleye,Adekunle; Tardif,Marcel, Series arc detection.
상세보기
Finlay, Sr.,David A.; Morgan,Kent; Richards,Jeffrey C., Shorted SCR lockout and indication.
상세보기
Radosavljevic, Dejan; Weeks, Richard, Shuttered receptacle for a protective device.
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Emery Franklin T. (Pittsburgh PA) Harrold Ronald T. (Murrysville Boro PA), System and method for detecting arcing in dynamoelectric machines.
상세보기
Restrepo,Carlos; Henson,Jeremy, Systems, devices, and methods for detecting arcs.
상세보기
Clunn Robert Henry, Test circuit for an AFCI/GFCI circuit breaker.
상세보기
Mackenzie Raymond Warren, Test circuit for verifying operation of an arc fault detector.
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Smith, Jeffrey L., Test instrument for arc fault circuit interrupters.
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Andy A. Haun ; Brian G. Grattan ; Kon B. Wong ; Robert F. Dvorak ; Gary W. Scott, Test, reset and communications operations in an ARC fault circuit interrupter with optional memory and/or backup power.
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Schmalz, Steven C.; Walz, Michael F.; McCormick, James M., Tester for a plurality of circuit breakers having a range of rated currents and multiple trip functions.
상세보기
Tallman, David M.; Murphy, William J.; Elms, Robert T., Testing device for detecting and locating arc faults in an electrical system.
상세보기
Tennies Charles J. (Waukesha WI) Beihoff Bruce C. (Wauwatosa WI) Hansen James E. (Oak Creek WI), Timing window arc detection.
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Spencer George A. (1909 Fresno Rd. Plano TX 75074), Trip delay override for electrical circuit breakers.
상세보기
Macbeth, Bruce F., Two winding resonating arc fault sensor which boosts arc fault signals while rejecting arc mimicking noise.
상세보기
Macbeth, Bruce F., Two winding resonating arc fault sensor which boosts arc fault signals while rejecting arc mimicking noise.
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Dollar, II, Charles Randall, Vehicle electrical system arc detection apparatus and method.
상세보기
Morgan,Kent; Richards,Jeffrey C.; Packard,Thomas N., Wiring device with multi-shot miswire.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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High speed controllable load 원문보기

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