초록 ▼

A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the fir

A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

대표청구항 ▼

1. A delay circuit which is reconfigurable and is included in a delay monitor circuit for measuring a delay in a signal transmission time in an integrated circuit, the delay circuit comprising: an input node for inputting an input signal;an output node for outputting an output signal;a first inversi

1. A delay circuit which is reconfigurable and is included in a delay monitor circuit for measuring a delay in a signal transmission time in an integrated circuit, the delay circuit comprising: an input node for inputting an input signal;an output node for outputting an output signal;a first inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect a power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect a ground potential to the output node when being turned on based on the input signal;a second inversion circuit including a serial circuit which comprises a pull-up circuit adapted to connect the power supply potential to the output node when being turned on based on the input signal, and a pull-down circuit adapted to connect the ground potential to the output node when being turned on based on the input signal;a first pass transistor connected in series to the pull-up circuit in the first inversion circuit, between the power supply potential and the output node;a second pass transistor connected in series to the pull-down circuit in the first inversion logic circuit, between the ground potential and the output node;a third pass transistor connected in series between the input node and an input of the pull-up circuit in the second inversion circuit; anda fourth pass transistor connected in series between the input node and an input of the pull-down circuit in the second inversion circuit,wherein a control signal applied to a gate of the third pass transistor controls the third pass transistor independently of a control signal applied to a gate of the fourth pass transistor, and wherein a delay characteristic of the reconfigurable delay circuit is changed by a combination of control signals applied to gates of the first to fourth pass transistors. 2. The delay circuit according to claim 1, wherein at least a fifth pass transistor is connected in parallel to the third pass transistor, and at least a sixth pass transistor is connected in parallel to the fourth pass transistor. 3. The delay circuit according to claim 1, further comprising a fifth pass transistor connected between the power supply potential and the pull-up circuit in the second inversion circuit, anda sixth pass transistor connected between the ground potential and the pull-down circuit in the second inversion circuit. 4. The delay circuit according to claim 1, further comprising a fifth pass transistor connected between the power supply potential and a control input of the pull-up circuit in the second inversion circuit, anda sixth pass transistor connected between the ground potential and a control input of the pull-down circuit in the second inversion circuit. 5. The delay circuit according to claim 1, wherein the combination of control signals include one or more ofa combination of control signals for turning on the first and second pass transistors and for turning off the third and fourth pass transistors,a combination of control signals for turning on the first and fourth pass transistors and for turning off the second and third pass transistors, anda combination of control signals for turning on the second and third pass transistors and for turning off the first and fourth pass transistors. 6. The delay circuit according to claim 1, wherein the first pass transistor is connected in series between the power supply potential and the pull-up circuit in the first inversion circuit, and the second pass transistor is connected in series between the ground potential and the pull-down circuit in the first inversion circuit. 7. The delay circuit according to claim 1, wherein the first pass transistor is connected in series between the output node and the pull-up circuit in the first inversion circuit, and the second pass transistor is connected in series between the output node and the pull-down circuit in the first inversion circuit. 8. The delay circuit according to claim 1, wherein the pull-up circuit of the first inversion circuit, the pull-up circuit of the second inversion circuit, and the third pass transistor are each a pMOS transistor, and the pull-down circuit of the first inversion circuit, the pull-down circuit of the second inversion circuit, and the fourth pass transistor are each an nMOS transistor. 9. The delay circuit according to claim 1, further comprising: multiple delay circuits connected in series to each other in multiple stages. 10. The delay circuit according to claim 9, wherein an output of the delay circuit in a last stage of the multiple stages is fed back to an input of the delay circuit in a first stage of the multiple stages. 11. The delay circuit according to claim 9, further comprising: a compensation circuit for compensating a variation in the characteristics of circuit elements in an integrated circuit, based on a delay of signal transmission measured by the delay circuit. 12. The delay circuit according to claim 11, wherein the circuit elements are transistors, and the compensation circuit is adapted to compensate the characteristics of the transistors by changing a substrate voltage for the transistors based on the measured delay of signal transmission. 13. A method for measuring a variation in characteristics of circuit elements in an integrated circuit using the delay circuit according to claim 9, setting the control signals for each stage in such a way as to make the delay circuit in a specific stage have a configuration different from configurations of the delay circuits in the other stages than the specific stage, and applying the set control signals to the pass transistors;measuring an output of the delay monitor circuit, with the control signals being applied to the pass transistors;repeating the setting the control signals and the measuring an output of the delay circuit while sequentially shifting the specific stage; andmeasuring a variation in the characteristics of the circuit elements in a chip on which the integrated circuit is formed, based on a result of the measurement obtained in the repeating. 14. A method for measuring a variation in characteristics of circuit elements among semiconductor chips on each of which an integrated circuit is formed using the delay circuit according to claim 9, the method comprising:setting the control signals for each stage in such a way as to make the delay circuits in all the stages have the same configuration and applying the set control signals to the pass transistors;measuring an output of the delay circuit, with the control signals being applied to the pass transistors; andmeasuring a variation in the characteristics of the circuit elements, among the chips on each of which the integrated circuit is formed, based on a result of the measurement obtained in measuring an output of the delay circuit. 15. A method for measuring a variation in characteristics of circuit elements in an integrated circuit using the delay circuit according to claim 2, wherein the delay circuit comprises multiple delay circuits connected in series to each other in multiple stages,the method comprising:setting the control signals for each stage in such a way as to make the delay circuit in a specific stage have a configuration different from configurations of the delay circuits in the other stages than the specific stage, and applying the set control signals to the pass transistors;measuring an output of the delay circuit, with the control signals being applied to the pass transistors;repeating the setting the control signals and the measuring an output of the delay circuit, while sequentially shifting the specific stage; andmeasuring a variation in the characteristics of the circuit elements in the chip on which the integrated circuit is formed, based on a result of the measurement obtained in the repeating,the measuring an output of the delay circuit includesturning on the third pass transistor while turning off the fifth transistor, and measuring an output of the delay circuit, for the specific stage,turning off the third pass transistor while turning on the fifth pass transistor, and measuring the output of the delay circuit, for the specific stage, andcalculating a difference between a result of the measurement obtained with the third pass transistor turned on and the fifth pass transistor turned off and a result of the measurement obtained with the third pass transistor turned off and the fifth pass transistor turned on. 16. A method for measuring a variation in characteristics of circuit elements in an integrated circuit using the delay circuit according to claim 2, wherein the delay circuit comprises multiple delay circuits connected in series to each other in multiple stages,the method comprising:setting the control signals for each stage in such a way as to make the delay circuit in a specific stage have a configuration different from configurations of the delay circuits in the other stages than the specific stage, and applying the set control signals to the pass transistors;measuring an output of the delay circuit, with the control signals being applied to the control signals to the pass transistors;repeating the setting the control signals and applying the set control signals and the measuring an output of the delay circuit, while sequentially shifting the specific stage; andmeasuring a variation in the characteristics of the circuit elements in a chip on which the integrated circuit is formed, based on a result of the measurement obtained in the repeating;the measuring an output of the delay circuit includesturning on the fourth pass transistor while turning off the sixth transistor, and measuring an output of the delay circuit, for the specific stage,turning off the fourth pass transistor while turning on the sixth pass transistor, and measuring the output of the delay circuit, for the specific stage, andcalculating a difference between a result of the measurement obtained with the fourth pass transistor turned on and the sixth pass transistor turned off and a result of the measurement obtained with the fourth pass transistor turned off and the sixth pass transistor turned on. 17. The method according to claim 13, further comprising: compensating the characteristics of the circuit elements based on the measured variation. 18. The method according to claim 14, further comprising: compensating the characteristics of the circuit elements based on the measured variation. 19. The method according to claim 15, further comprising: compensating the characteristics of the circuit elements based on the measured variation. 20. The method according to claim 16, further comprising: compensating the characteristics of the circuit elements based on the measured variation.