Semiconductor apparatus, routing module, and control method of semiconductor apparatus
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/173
H03K-019/177
출원번호
US-0255583
(2016-09-02)
등록번호
US-9900011
(2018-02-20)
발명자
/ 주소
Inoue, Kazuki
Oikawa, Kohei
Miyamoto, Yukimasa
Hatsuda, Kosuke
Nomura, Shuou
Suzuki, Kojiro
출원인 / 주소
Kabushiki Kaisha Toshiba
대리인 / 주소
White & Case LLP
인용정보
피인용 횟수 :
0인용 특허 :
7
초록▼
According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The swi
According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.
대표청구항▼
1. A semiconductor apparatus comprising a block including a logic circuit and a routing module, and a controller, the routing module being arranged to build a transmission route for outputting signals input from first elements to second elements, the first elements including the logic circuit and el
1. A semiconductor apparatus comprising a block including a logic circuit and a routing module, and a controller, the routing module being arranged to build a transmission route for outputting signals input from first elements to second elements, the first elements including the logic circuit and elements connected to the block, the second elements including the logic circuit and elements connected to the block, the routing module including:a plurality of first wiring lines respectively having input ends, into one of which a signal from one of the first elements is to be input;a plurality of second wiring lines respectively having output ends, from one of which a signal is to be output to one of the second elements;switches, one of the switches arranged to perform connection and disconnection between one of the first wiring lines and one of the second wiring lines; anda wiring line switching circuit arranged to switch connections between the input ends and the first elements or switch connections between the output ends and the second elements,wherein the controller is arranged to control driving of the switches and the wiring line switching circuit. 2. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit is arranged to switch one of the input ends to connect with one of the first elements, and the wiring line switching circuit is interposed between all input signal lines from the first elements and the input ends. 3. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit is arranged to switch one of the output ends to connect with one of the second elements, and the wiring line switching circuit is interposed between the output ends and all output signal lines to the second elements. 4. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit includes a first circuit arranged to switch one of the input ends to connect with one of the first elements, and a second circuit arranged to switch one of the output ends to connect with one of the second elements, the first circuit is interposed between all input signal lines from the first elements and the input ends, andthe second circuit is interposed between the output ends and all output signal lines to the second elements. 5. The semiconductor apparatus according to claim 1, wherein the controller is arranged to control driving of the switches and the wiring line switching circuit, based on fault information about the switches. 6. The semiconductor apparatus according to claim 1, comprising a memory that holds fault information about the switches, wherein the controller is arranged to control driving of the switches and the wiring line switching circuit, based on the fault information held in the memory. 7. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit includes links capable of connecting one of the first elements to one of all the input ends. 8. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit includes links capable of connecting one of the first elements to one of two input ends disposed adjacent to one another. 9. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit includes links capable of connecting one of the first elements to one of three input ends disposed adjacent to one another. 10. The semiconductor apparatus according to claim 1, wherein the wiring line switching circuit includes a plurality of subsets, and is arranged to switch a wiring line for transmitting the signal in one of the subsets. 11. The semiconductor apparatus according to claim 1, wherein the routing module further includes a first spare wiring line having an input end, and wherein the wiring line switching circuit is arranged to switch connection and disconnection between the first elements and the input end of the first spare wiring line. 12. The semiconductor apparatus according to claim 11, wherein the wiring line switching circuit includes links capable of connecting one of the first elements to one of the input ends of the plurality of first wiring lines, and a link capable of connecting this one first element to the input end of the first spare wiring line. 13. The semiconductor apparatus according to claim 1, wherein the routing module further includes a second spare wiring line having an output end, and wherein the wiring line switching circuit is arranged to switch connection and disconnection between the second elements and the output end of the second spare wiring line. 14. The semiconductor apparatus according to claim 1, wherein a plurality of blocks are arrayed in a two-dimensional state, in which routing modules of adjacent ones of the plurality of blocks are connected to one another. 15. A routing module included in a logic block that constitutes a semiconductor apparatus, the routing module being arranged to build a transmission route for outputting signals input from first elements to second elements, the first elements including a logic circuit included in the logic block and elements connected to the logic block, the second elements including a logic circuit included in the logic block and elements connected to the logic block, the routing module comprising:a plurality of first wiring lines respectively having input ends, into one of which a signal from one of the first elements is to be input;a plurality of second wiring lines respectively having output ends, from one of which a signal is to be output to one of the second elements;switches, one of the switches arranged to perform connection and disconnection between one of the first wiring lines and one of the second wiring lines; anda wiring line switching circuit arranged to switch connections between the input ends and the first elements or switch connections between the output ends and the second elements. 16. The routing module according to claim 15, wherein the wiring line switching circuit is arranged to switch one of the input ends to connect with one of the first elements, and the wiring line switching circuit is interposed between all input signal lines from the first elements and the input ends. 17. The routing module according to claim 15, wherein the wiring line switching circuit is arranged to switch one of the output ends to connect with one of the second elements, and the wiring line switching circuit is interposed between the output ends and all output signal lines to the second elements. 18. The routing module according to claim 15, wherein the wiring line switching circuit includes a plurality of subsets, and is arranged to switch connections between the input ends and the first elements in one of the subsets or switch connections between the output ends and the second elements in one of the subsets. 19. A control method of a semiconductor apparatus including a block, the block including a logic circuit and a routing module, the routing module being arranged to build a transmission route for outputting signals input from first elements to second elements, the first elements including the logic circuit and elements connected to the block, the second elements including the logic circuit and elements connected to the block, the control method comprising:obtaining first information for controlling driving of switches and a wiring line switching circuit, one of the switches being arranged to perform connection and disconnection between one of first wiring lines and one of second wiring lines, the wiring line switching circuit being arranged to switch connections between the input ends and the first elements or switch connections between the output ends and the second elements, a signal being to be input from one of the first elements into one of the first wiring lines, a signal being to be output from one of the second wiring lines to one of the second elements;correcting the first information, based on second information about occurrence of a fault in the switches; andcontrolling driving of the switches and the wiring line switching circuit, based on the first information in a corrected state. 20. The control method of a semiconductor apparatus according to claim 19, comprising reading out the second information from a memory included in the semiconductor apparatus.
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이 특허에 인용된 특허 (7)
Zhao, Jun, Congestion estimation based on routing resources of programmable logic devices.
Bruck Jehoshua (Palo Alto CA) Cypher Robert E. (Los Gatos CA) Ho Ching-Tien (San Jose CA), Method and apparatus for a fault-tolerant mesh with spare nodes.
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