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Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
  • H01L-027/00
  • G03F-001/00
  • G03F-007/00
  • G03F-001/70
  • G03F-007/20
  • H01L-027/02
출원번호 US-0675516 (2015-03-31)
등록번호 US-9904756 (2018-02-27)
발명자 / 주소
  • Ruehl, Roland
  • Arkhipov, Alexandre
  • Powell, Giles V.
  • Sharma, Karun
출원인 / 주소
  • Cadence Design Systems, Inc.
대리인 / 주소
    Vista IP Law Group, LLP
인용정보 피인용 횟수 : 3  인용 특허 : 41

초록

Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a s

대표청구항

1. A computer implemented method for implementing DRC (design rule check) clean multi-patterning process nodes with lateral fills in an electronic design, comprising: identifying legal track patterns and one or more design rules that govern multiple patterning and the legal track patterns by accessi

이 특허에 인용된 특허 (41)

  1. Yoel, David William; Littlefield, John E.; Hill, Robert Duane, Airborne widefield airspace imaging and monitoring.
  2. Friedberg, Paul David; Gao, Tong; Fang, Weiping; Tong, Yang-Shan, Automated repair method and system for double patterning conflicts.
  3. Birch, Jeremy; Waller, Mark; Balsdon, Graham, Automatically routing nets with variable spacing.
  4. Birch, Jeremy, High-speed shape-based router.
  5. Sharma, Puneet; Abadir, Magdy S.; Warrick, Scott P., Integrated circuit device with reduced leakage and method therefor.
  6. Bosshart, Patrick W., Interactive routing editor with symbolic and geometric views for integrated circuit layout.
  7. Chase, Scott; Dai, Zuo; Liu, Dick; Su, Ming, Low-overhead multi-patterning design rule check.
  8. Chen, Huang-Yu; Fan, Fang-Yu; Hou, Yuan-Te; Lu, Lee-Chung; Liu, Ru-Gun; Hsieh, Ken-Hsien; Song, Lee Fung; Huang, Wen-Chun; Tien, Li-Chun, Method and apparatus for achieving multiple patterning technology compliant design layout.
  9. Malik,Shobhit, Method and apparatus for inserting extra tracks during library architecture migration.
  10. Blatchford, James Walter, Method for ensuring DPT compliance with autorouted metal layers.
  11. Cai Yang, Method for handling variable width wires in a grid-based channel router.
  12. Schultz, Richard; Pattison, James, Method of creating photolithographic masks for semiconductor device features with reduced design rule violations.
  13. Groeneveld Patrick R. ; van Ginneken Lukas P. P. P., Method of designing a constraint-driven integrated circuit layout.
  14. Lee, Hyun-Jong; Choi, Soo-Han; Do, Jung-Ho; Park, Chul-Hong; Sim, Sang-Pil, Method of forming a pattern.
  15. Park, Dong-woon; Lee, Hyun-jong; Choi, Si-young; Bae, Yong-kug, Method of forming pattern, reticle, and computer readable medium for storing program for forming pattern.
  16. Melzner, Hanno; Rizzo, Olivier; Herry, Jacques, Method of making in an integrated circuit including simplifying metal shapes.
  17. Roy Kaushik (West Lafayette IN) Nag Sudip K. (Pittsburgh PA), Method of segmenting an FPGA channel architecture for maximum routability and performance.
  18. Lee, Yinnie; Markham, Jeffrey; Ruehl, Roland; Sharma, Karun, Method, system, and computer program product for implementing repetitive track patterns for electronic circuit designs.
  19. Lee, Yinnie; Markham, Jeffrey; Ruehl, Roland; Sharma, Karun, Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designs.
  20. Cao, Min; Ruehl, Roland, Method, system, and program product for interactive checking for double pattern lithography violations.
  21. Reed, Brian; Smayling, Michael C.; Hong, Joseph N.; Fairbanks, Stephen; Becker, Scott T., Methods for defining and utilizing sub-resolution features in linear topology.
  22. Yuan, Lei; Choi, Soo Han; Kye, Jongwook; Levinson, Harry J., Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules.
  23. Salowe, Jeffrey S., Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs.
  24. Salowe, Jeffrey S., Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design.
  25. Sun, Ganping; Huang, Pujiang; Li, Jianmin; Arifin, Taufik, Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques.
  26. Li, Jianmin; Chen, Jing; Zhao, Guowei; Arifin, Taufik; Huang, Yuan; Kim, Soohong A.; Gerousis, Vassilios; Zhang, Shuo; Chen, Dahe, Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques.
  27. Salowe, Jeffrey, Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks.
  28. Salowe, Jeffrey; Cao, Min; Ruehl, Roland; Markham, Jeffrey, Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns.
  29. Powell, Giles V.; Arkhipov, Alexandre; Ruehl, Roland; Sharma, Karun, Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques.
  30. Arkhipov, Alexandre; Powell, Giles V.; Ruehl, Roland; Sharma, Karun, Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs.
  31. Lee, Hui Yu; Chang, Chi-Wen; Yang, Chih Ming; Liu, Ya Yun; Cheng, Yi-Kan, Multi-patterning system and method using pre-coloring or locked patterns.
  32. Kornachuk, Stephen; Lambert, Carole; Mali, James; Reed, Brian; Becker, Scott T., Optimizing layout of irregular structures in regular layout context.
  33. Bendicksen, Jon; Bishop, Randy; Dai, Zuo; Hapli, John; Liu, Dick; Su, Ming, Real time DRC assistance for manual layout editing.
  34. Gray, Michael S.; Guzowski, Matthew T.; Ivrii, Alexander; Liebmann, Lars W.; McCullen, Kevin W.; Tellez, Gustavo E.; Gester, Michael, Reducing color conflicts in triple patterning lithography.
  35. Ushiyama, Kenichi; Ichinose, Shigenori, Semiconductor integrated circuit having reduced cross-talk noise.
  36. Wang, Lynn; Madhavan, Sriram; Capodieci, Luigi, Stitch insertion for reducing color density differences in double patterning technology (DPT).
  37. Pierrat, Christophe, System and method for applying phase effects of mask diffraction patterns.
  38. Graur,Ioana; Kim,Young O.; Lavin,Mark A.; Liebmann,Lars W., System for coloring a partially colored design in an alternating phase shift mask.
  39. Peng, Yung-Chow; Chou, Wen-Shen; Horng, Jaw-Juinn, System for designing a semiconductor device, device made, and method of using the system.
  40. Hsu, Chin-Hsiung; Hou, Yuan-Te; Chen, Wen-Hao, Systems and methods for designing layouts for semiconductor device fabrication.
  41. Buehler,Markus T.; Cohn,John M.; Hathaway,David J.; Hibbeler,Jason D.; Koehl,Juergen, Use of redundant routes to increase the yield and reliability of a VLSI layout.

이 특허를 인용한 특허 (3)

  1. Pandey, Diwesh; Schulte, Christian; Tellez, Gustavo E, Capacity model for global routing.
  2. Ginetti, Arnold, Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design.
  3. Ginetti, Arnold, Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design.
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